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| author | Huacai Chen <chenhc@lemote.com> | 2017-03-16 13:00:25 (GMT) |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2017-04-12 10:41:14 (GMT) |
| commit | 186fb3c52e39e41977fd7227a45bcd0877af790b (patch) | |
| tree | e1c4510b91f77153a2770acadf5b2b6304cf8a8b /arch | |
| parent | 3d5e13d891b0e7f4b7eee97aea1c15037a994d68 (diff) | |
| download | linux-186fb3c52e39e41977fd7227a45bcd0877af790b.tar.xz | |
MIPS: Add MIPS_CPU_FTLB for Loongson-3A R2
commit 033cffeedbd11c140952b98e8639bf652091a17d upstream.
Loongson-3A R2 and newer CPU have FTLB, but Config0.MT is 1, so add
MIPS_CPU_FTLB to the CPU options.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J . Hill <Steven.Hill@caviumnetworks.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/15752/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/kernel/cpu-probe.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index dd31754..921211b 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1824,7 +1824,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) } decode_configs(c); - c->options |= MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; + c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; c->writecombine = _CACHE_UNCACHED_ACCELERATED; break; default: |