diff options
| author | Kumar Gala <galak@kernel.crashing.org> | 2008-06-19 14:40:31 (GMT) |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2008-06-26 06:49:03 (GMT) |
| commit | aba11fc50c925bbd6fb25d54eae2f86277a3b107 (patch) | |
| tree | 52c85a46371ca4ef05042600507ecd5bdcfa2842 /arch | |
| parent | fc4033b2f8b1482022bff3d05505a1b1631bb6de (diff) | |
| download | linux-aba11fc50c925bbd6fb25d54eae2f86277a3b107.tar.xz | |
powerpc/e500mc: flush L2 on NAP for e500mc
If we have an L2CSR register (e500mc) we need to flush the L2 before going
to nap. We use the HW flush mechanism provided in that register.
The code reuses the CPU_FTR_604_PERF_MON bit as it is no longer used by
any code in the kernel. Additionally we didn't reuse the exist L2CR
feature bit as this is intended for the 7xxx L2CR register and L2CSR
is part of the new Freescale "Book-E" registers.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/kernel/idle_e500.S | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/idle_e500.S b/arch/powerpc/kernel/idle_e500.S index 267adec..0630403 100644 --- a/arch/powerpc/kernel/idle_e500.S +++ b/arch/powerpc/kernel/idle_e500.S @@ -47,6 +47,15 @@ BEGIN_FTR_SECTION mtlr r0 lis r3,HID0_NAP@h END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) +BEGIN_FTR_SECTION + msync + li r7,L2CSR0_L2FL@l + mtspr SPRN_L2CSR0,r7 +2: + mfspr r7,SPRN_L2CSR0 + andi. r4,r7,L2CSR0_L2FL@l + bne 2b +END_FTR_SECTION_IFSET(CPU_FTR_L2CSR|CPU_FTR_CAN_NAP) 1: /* Go to NAP or DOZE now */ mfspr r4,SPRN_HID0 |