diff options
| author | Thomas Gleixner <tglx@linutronix.de> | 2006-07-01 21:32:14 (GMT) |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-07-01 21:32:14 (GMT) |
| commit | c4bfa28aec58c588de55babe99f4c172ec534704 (patch) | |
| tree | dc105fc1c44b26e19a82b076b37370812192bd0c /arch | |
| parent | 4a2581a080098ca3a0c4e416d7a282e96c75ebf8 (diff) | |
| download | linux-c4bfa28aec58c588de55babe99f4c172ec534704.tar.xz | |
[ARM] 3686/1: ARM: arm/common: convert irq handling
Patch from Thomas Gleixner
From: Thomas Gleixner <tglx@linutronix.de>
Convert the files in arch/arm/common to use the generic
irq handling functions.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/common/gic.c | 18 | ||||
| -rw-r--r-- | arch/arm/common/sa1111.c | 6 | ||||
| -rw-r--r-- | arch/arm/common/time-acorn.c | 1 |
3 files changed, 20 insertions, 5 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index c02dc81..f3c1ebf 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -33,6 +33,7 @@ static void __iomem *gic_dist_base; static void __iomem *gic_cpu_base; +static DEFINE_SPINLOCK(irq_controller_lock); /* * Routines to acknowledge, disable and enable interrupts @@ -52,32 +53,45 @@ static void __iomem *gic_cpu_base; static void gic_ack_irq(unsigned int irq) { u32 mask = 1 << (irq % 32); + + spin_lock(&irq_controller_lock); writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4); writel(irq, gic_cpu_base + GIC_CPU_EOI); + spin_unlock(&irq_controller_lock); } static void gic_mask_irq(unsigned int irq) { u32 mask = 1 << (irq % 32); + + spin_lock(&irq_controller_lock); writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4); + spin_unlock(&irq_controller_lock); } static void gic_unmask_irq(unsigned int irq) { u32 mask = 1 << (irq % 32); + + spin_lock(&irq_controller_lock); writel(mask, gic_dist_base + GIC_DIST_ENABLE_SET + (irq / 32) * 4); + spin_unlock(&irq_controller_lock); } #ifdef CONFIG_SMP -static void gic_set_cpu(struct irqdesc *desc, unsigned int irq, unsigned int cpu) +static void gic_set_cpu(unsigned int irq, cpumask_t mask_val) { void __iomem *reg = gic_dist_base + GIC_DIST_TARGET + (irq & ~3); unsigned int shift = (irq % 4) * 8; + unsigned int cpu = first_cpu(mask_val); u32 val; + spin_lock(&irq_controller_lock); + irq_desc[irq].cpu = cpu; val = readl(reg) & ~(0xff << shift); val |= 1 << (cpu + shift); writel(val, reg); + spin_unlock(&irq_controller_lock); } #endif @@ -86,7 +100,7 @@ static struct irqchip gic_chip = { .mask = gic_mask_irq, .unmask = gic_unmask_irq, #ifdef CONFIG_SMP - .set_cpu = gic_set_cpu, + .set_affinity = gic_set_cpu, #endif }; diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index fe06a36..1cdb26a 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -150,7 +150,7 @@ static void sa1111_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs) { unsigned int stat0, stat1, i; - void __iomem *base = desc->data; + void __iomem *base = get_irq_data(irq); stat0 = sa1111_readl(base + SA1111_INTSTATCLR0); stat1 = sa1111_readl(base + SA1111_INTSTATCLR1); @@ -168,11 +168,11 @@ sa1111_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs) for (i = IRQ_SA1111_START; stat0; i++, stat0 >>= 1) if (stat0 & 1) - do_edge_IRQ(i, irq_desc + i, regs); + handle_edge_irq(i, irq_desc + i, regs); for (i = IRQ_SA1111_START + 32; stat1; i++, stat1 >>= 1) if (stat1 & 1) - do_edge_IRQ(i, irq_desc + i, regs); + handle_edge_irq(i, irq_desc + i, regs); /* For level-based interrupts */ desc->chip->unmask(irq); diff --git a/arch/arm/common/time-acorn.c b/arch/arm/common/time-acorn.c index 486add8..31b65e2 100644 --- a/arch/arm/common/time-acorn.c +++ b/arch/arm/common/time-acorn.c @@ -16,6 +16,7 @@ #include <linux/timex.h> #include <linux/init.h> #include <linux/interrupt.h> +#include <linux/irq.h> #include <asm/hardware.h> #include <asm/io.h> |