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| author | Catalin Marinas <catalin.marinas@arm.com> | 2013-04-24 13:47:02 (GMT) |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2013-04-25 16:45:48 (GMT) |
| commit | 5108c67c376b3ee59cc7fbe46eaba481eb3419aa (patch) | |
| tree | 0f2515769d1ceecc8f55380aff228c54929275e1 /block | |
| parent | 4b3ea2e04d2b8b37c5bc472f710d706b42e4fa06 (diff) | |
| download | linux-5108c67c376b3ee59cc7fbe46eaba481eb3419aa.tar.xz | |
arm64: Execute DSB during thread switching for TLB/cache maintenance
The DSB following TLB or cache maintenance ops must be run on the same
CPU. With kernel preemption enabled or for user-space cache maintenance
this may not be the case. This patch adds an explicit DSB in the
__switch_to() function.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'block')
0 files changed, 0 insertions, 0 deletions