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| author | Thierry Reding <thierry.reding@gmail.com> | 2013-10-29 15:51:12 (GMT) |
|---|---|---|
| committer | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-11-26 16:46:57 (GMT) |
| commit | c04bf559264de4f986463c639fabef2028542924 (patch) | |
| tree | 30bfdeed6283bfb603cad43a5519a09c75570dc4 /drivers/block | |
| parent | 43e36a9646ec7d0180d638c095cca36484cc6f82 (diff) | |
| download | linux-c04bf559264de4f986463c639fabef2028542924.tar.xz | |
clk: tegra: Properly setup PWM clock on Tegra30
The clock for the PWM controller is slightly different from other
peripheral clocks on Tegra30. The clock source mux field start at
bit position 28 rather than 30.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/block')
0 files changed, 0 insertions, 0 deletions