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author | Liu Ying <Ying.Liu@freescale.com> | 2015-02-12 06:01:30 (GMT) |
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committer | Shawn Guo <shawn.guo@linaro.org> | 2015-03-02 12:52:16 (GMT) |
commit | e654df7a1a4843429b5d1d6ee40cac9ecef75304 (patch) | |
tree | 60111ee985afb8c61914d195af3c0d9a8e8f24ec /drivers/bus | |
parent | 5ccc248cc53708337a2bfe4ea380c20948e8bbed (diff) | |
download | linux-e654df7a1a4843429b5d1d6ee40cac9ecef75304.tar.xz |
ARM: imx6q: clk: Add support for mipi_ipg clock as a shared clock gate
The CG8 field of the CCM CCGR3 register is the 'mipi_core_cfg' gate clock,
according to the i.MX6q/sdl reference manuals. This clock is actually the
gate for several clocks, including the ipg clock's output. The MIPI DSI host
controller embedded in the i.MX6q/sdl SoCs takes the ipg clock as the pclk -
the APB clock signal . In order to gate/ungate the ipg clock, this patch adds
a new shared clock gate named as "mipi_ipg".
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'drivers/bus')
0 files changed, 0 insertions, 0 deletions