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authorThierry Reding <treding@nvidia.com>2015-04-20 13:10:43 (GMT)
committerThierry Reding <treding@nvidia.com>2016-04-28 10:41:49 (GMT)
commiteede7113aabd3f40f8d9c32b1690f2859fcb101a (patch)
treeffa6885caeb0e7e1a1e1a64161a4082771cceedc /drivers/char/nwbutton.c
parent98c4b3661b5aee0e583d17d6304f6489c0f41155 (diff)
downloadlinux-eede7113aabd3f40f8d9c32b1690f2859fcb101a.tar.xz
clk: tegra: dpaux and dpaux1 are fixed factor clocks
The dpaux (on Tegra124 and Tegra210) and dpaux1 (on Tegra210) are fixed factor clocks (1:17) and derived from pll_p_out0 (pll_p). They also have a gate bit in the peripheral clock registers. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/char/nwbutton.c')
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