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| author | Kevin Cernekee <cernekee@chromium.org> | 2015-05-26 22:01:09 (GMT) |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2015-06-04 19:43:39 (GMT) |
| commit | 17bfa3f7b3cd07e92b41ce7b5bea2dd8c8e2a8c3 (patch) | |
| tree | c24c733c8b2d1eaffb88bfdcc2054669e73af989 /drivers/clk/at91/clk-slow.c | |
| parent | e0b7a79524771ad368abefbbcbd73f130f8e500e (diff) | |
| download | linux-17bfa3f7b3cd07e92b41ce7b5bea2dd8c8e2a8c3.tar.xz | |
clk: pistachio: Add sanity checks on PLL configuration
When setting the PLL rates, check that:
- VCO is within range
- PFD is within range
- PLL is disabled when postdiv is changed
- postdiv2 <= postdiv1
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Kevin Cernekee <cernekee@chromium.org>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/at91/clk-slow.c')
0 files changed, 0 insertions, 0 deletions