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| author | Thierry Reding <thierry.reding@gmail.com> | 2013-11-18 15:11:36 (GMT) |
|---|---|---|
| committer | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-11-26 16:46:58 (GMT) |
| commit | 39409aa4244f22eae3fa8f8db4b0cf9466b73c44 (patch) | |
| tree | 6c488cf25b168ad13342a24ea69fac2ddcc92679 /drivers/clk/tegra/clk-pll.c | |
| parent | 5ab5d4048e6ed8811245a4ea45264456c180545e (diff) | |
| download | linux-39409aa4244f22eae3fa8f8db4b0cf9466b73c44.tar.xz | |
clk: tegra: Initialize DSI low-power clocks
The low-power DSI clocks are used during host-driven transactions on the
DSI bus. Documentation recommends that they be children of PLLP and run
at a frequency of at least 52 MHz.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-pll.c')
0 files changed, 0 insertions, 0 deletions