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| author | Rhyland Klein <rklein@nvidia.com> | 2016-01-14 19:24:35 (GMT) |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-02-02 14:49:24 (GMT) |
| commit | 3dad5c5fa1d24c3bbb3e9e8ac0c52f35e045b807 (patch) | |
| tree | d3b7c9b1ec316b1bc5838f754c43f8b8a3250049 /drivers/clk/tegra/clk-pll.c | |
| parent | 3eb61566a6efc5a56ebe1e6b86519bc5e0b39003 (diff) | |
| download | linux-3dad5c5fa1d24c3bbb3e9e8ac0c52f35e045b807.tar.xz | |
clk: tegra: Fix pllx dyn step calculation
The logic for calculating the input rate used when figuring out the
proper dynamic steps for pllx was incorrect. It is supposed to be
calculated using parent_rate / m but it was just using the parent rate
directly, therefore using the wrong step values.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-pll.c')
0 files changed, 0 insertions, 0 deletions