diff options
| author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-09-09 10:22:55 (GMT) |
|---|---|---|
| committer | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-11-26 16:46:51 (GMT) |
| commit | 798e910bee3f9ad69a8b16d7e705086852d9f2de (patch) | |
| tree | dedd66ad923319d1125350fcc7b6fb54711b41fb /drivers/clk/tegra/clk.h | |
| parent | 540fc26a02a950a523a62a16d75b87f0e2103584 (diff) | |
| download | linux-798e910bee3f9ad69a8b16d7e705086852d9f2de.tar.xz | |
clk: tegra: Add support for PLLSS
Tegra124 introduces a new PLL type, PLLSS. Add support for it.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk.h')
| -rw-r--r-- | drivers/clk/tegra/clk.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 05abfc5..7f110ac 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -298,6 +298,11 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name, struct tegra_clk_pll_params *pll_params, spinlock_t *lock); +struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, + void __iomem *clk_base, unsigned long flags, + struct tegra_clk_pll_params *pll_params, + spinlock_t *lock); + /** * struct tegra_clk_pll_out - PLL divider down clock * |