diff options
| author | Icenowy Zheng <icenowy@aosc.xyz> | 2016-11-17 16:49:54 (GMT) |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-11-23 20:32:39 (GMT) |
| commit | 98fb2b95d293c4e29c35f188f7745a5e5db3db2d (patch) | |
| tree | 459c2e4bff8c7a72b8620d4a85c34ca83d8d7ff4 /drivers/clk | |
| parent | 95881a54b8b175be56adbcd86a473d8e8d5be2aa (diff) | |
| download | linux-98fb2b95d293c4e29c35f188f7745a5e5db3db2d.tar.xz | |
clk: sunxi-ng: enable so-said LDOs for A33 SoC's pll-mipi clock
In the user manual of A33 SoC, the bit 22 and 23 of pll-mipi control
register is called "LDO{1,2}_EN", and according to the BSP source code
from Allwinner [1], the LDOs are enabled during the clock's enabling
process.
The clock failed to generate output if the two LDOs are not enabled.
Add the two bits to the clock's gate bits, so that the LDOs are enabled
when the PLL is enabled.
[1] https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw5.c#L429
Fixes: d05c748bd730 ("clk: sunxi-ng: Add A33 CCU support")
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c index 96b40ca..9bd1f78 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c @@ -131,7 +131,7 @@ static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi", 8, 4, /* N */ 4, 2, /* K */ 0, 4, /* M */ - BIT(31), /* gate */ + BIT(31) | BIT(23) | BIT(22), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); |