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author | Elie De Brauwer <eliedebrauwer@gmail.com> | 2013-09-17 17:48:22 (GMT) |
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committer | David Woodhouse <David.Woodhouse@intel.com> | 2013-09-27 10:56:22 (GMT) |
commit | 2b468ef0e7959b703626b64c4d264ef822c9267a (patch) | |
tree | 7f8c4471558965162b2a8626f4fb288441462600 /drivers/cpufreq/intel_pstate.c | |
parent | 5cb1327172281cadb7ee8c5fa294d7ac8e09b8db (diff) | |
download | linux-2b468ef0e7959b703626b64c4d264ef822c9267a.tar.xz |
mtd: m25p80: Fix 4 byte addressing mode for Micron devices.
According to the datasheet for Micron n25q256a (N25Q256A13ESF40F) 4-byte
addressing mode should be entered as follows:
<quote>
To enter or exit the 4-byte address mode, the WRITE ENABLE command
must be executed to set the write enable latch bit to 1. (Note: The
WRITE ENABLE command must NOT be executed on the N25Q256A83ESF40x and
N25Q256A83E1240x devices.) S# must be driven LOW. The effect of the
command is immediate; after the command has been executed, the write
enable latch bit is cleared to 0.
</quote>
Micron's portable way to perform this for all types of Micron flash
is to first issue a write enable, then switch the addressing mode
followed by a write disable to avoid leaving the flash in a write-
able state.
Signed-off-by: Elie De Brauwer <eliedebrauwer@email.com>
[Brian: reworked a bit]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/cpufreq/intel_pstate.c')
0 files changed, 0 insertions, 0 deletions