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author | Horia Geantă <horia.geanta@nxp.com> | 2017-05-17 16:51:24 (GMT) |
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committer | Xie Xiaobo <xiaobo.xie@nxp.com> | 2017-09-25 07:25:23 (GMT) |
commit | df3d752f33b3427a2c493e45750905792d0f778a (patch) | |
tree | 46e053f541d9c2dc2c7fd54d94ec0904b5769987 /drivers/crypto/caam/jr.c | |
parent | 7f03c854c22676a8b7c0e964b37f0379ea0bf50d (diff) | |
download | linux-df3d752f33b3427a2c493e45750905792d0f778a.tar.xz |
crypto: caam/jr - add support for DPAA2 parts
Add support for using the caam/jr backend on DPAA2-based SoCs.
These have some particularities we have to account for:
-HW S/G format is different
-Management Complex (MC) firmware initializes / manages (partially)
the CAAM block: MCFGR, QI enablement in QICTL, RNG
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Diffstat (limited to 'drivers/crypto/caam/jr.c')
-rw-r--r-- | drivers/crypto/caam/jr.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c index 2763100..0eac1f8 100644 --- a/drivers/crypto/caam/jr.c +++ b/drivers/crypto/caam/jr.c @@ -9,6 +9,7 @@ #include <linux/of_address.h> #include "compat.h" +#include "ctrl.h" #include "regs.h" #include "jr.h" #include "desc.h" @@ -499,7 +500,11 @@ static int caam_jr_probe(struct platform_device *pdev) jrpriv->rregs = (struct caam_job_ring __iomem __force *)ctrl; if (sizeof(dma_addr_t) == sizeof(u64)) { - if (of_device_is_compatible(nprop, "fsl,sec-v5.0-job-ring")) + if (caam_dpaa2) + error = dma_set_mask_and_coherent(jrdev, + DMA_BIT_MASK(49)); + else if (of_device_is_compatible(nprop, + "fsl,sec-v5.0-job-ring")) error = dma_set_mask_and_coherent(jrdev, DMA_BIT_MASK(40)); else |