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| author | Alex Deucher <alexander.deucher@amd.com> | 2016-04-29 15:44:32 (GMT) |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2016-05-05 00:30:57 (GMT) |
| commit | a0cdef9e8234cd501d1ad1ea8517136087b3e60f (patch) | |
| tree | 0e2d7cb7af198d8c7ec8e48ac0afcd27b387fc88 /drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | |
| parent | bdf1ecea3c656acab45976ff7a6ba53b37cd7a1d (diff) | |
| download | linux-a0cdef9e8234cd501d1ad1ea8517136087b3e60f.tar.xz | |
drm/amdgpu/uvd6: add bypass support for fiji (v3)
Handle uvd clock bypass settings as part of clockgating
setup.
v2: fix gate logic
v3: fix header include
Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 5665a4f..d015cb0 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -31,6 +31,8 @@ #include "uvd/uvd_6_0_sh_mask.h" #include "oss/oss_2_0_d.h" #include "oss/oss_2_0_sh_mask.h" +#include "smu/smu_7_1_3_d.h" +#include "smu/smu_7_1_3_sh_mask.h" #include "vi.h" static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev); @@ -823,6 +825,20 @@ static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev) } #endif +static void uvd_v6_set_bypass_mode(struct amdgpu_device *adev, bool enable) +{ + u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); + + if (enable) + tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | + GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); + else + tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | + GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); + + WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); +} + static int uvd_v6_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) { @@ -830,6 +846,9 @@ static int uvd_v6_0_set_clockgating_state(void *handle, bool enable = (state == AMD_CG_STATE_GATE) ? true : false; static int curstate = -1; + if (adev->asic_type == CHIP_FIJI) + uvd_v6_set_bypass_mode(adev, enable); + if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) return 0; |