diff options
| author | Imre Deak <imre.deak@intel.com> | 2016-05-03 12:54:20 (GMT) |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2016-05-03 13:49:15 (GMT) |
| commit | 36579cb63b87b7a4406b9b19c8ff376ca701083b (patch) | |
| tree | 08a5555290f7b17085f9d3ae959197b642208e13 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 48e5d68d28f00c0cadac5a830980ff3222781abb (diff) | |
| download | linux-36579cb63b87b7a4406b9b19c8ff376ca701083b.tar.xz | |
drm/i915: Clean up L3 SQC register field definitions
No need for hard-coding the register value, the corresponding fields are
defined properly in BSpec.
No functional change.
v2:
- Rebased on BXT L3 SQC tuning patch merged meanwhile.
CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
Link: http://patchwork.freedesktop.org/patch/msgid/1462280061-1457-3-git-send-email-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fd19f57..543f440 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6091,8 +6091,8 @@ enum skl_disp_power_wells { #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 #define GEN8_L3SQCREG1 _MMIO(0xB100) -#define BDW_WA_L3SQCREG1_DEFAULT 0x784000 -#define BXT_WA_L3SQCREG1_DEFAULT 0xF84000 +#define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19) +#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14) #define GEN7_L3CNTLREG1 _MMIO(0xB01C) #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C |