diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-03-12 15:10:36 (GMT) |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-03-20 10:48:08 (GMT) |
| commit | ed4e9c1d46980e76254573ccd59efb3e8aec77d2 (patch) | |
| tree | 9e8c08bf1ae046a0af6438f2d76d9cffd41590f6 /drivers/gpu/drm/i915/intel_dp.c | |
| parent | bc27b7d3f096e88f9b6571965452925fc93f2ca3 (diff) | |
| download | linux-ed4e9c1d46980e76254573ccd59efb3e8aec77d2.tar.xz | |
drm/i915: Fix MST link rate handling
Now that intel_dp_max_link_bw() no longer considers the source
restrictions we may try to enable MST with 5.4GHz even when the source
doesn't support it. To fix that switch the code over to handle the link
rate in the same way as the SST code handles it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index aa3c678..c02e022 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -122,8 +122,8 @@ static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); static void vlv_steal_power_sequencer(struct drm_device *dev, enum pipe pipe); -int -intel_dp_max_link_bw(struct intel_dp *intel_dp) +static int +intel_dp_max_link_bw(struct intel_dp *intel_dp) { int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; @@ -1255,6 +1255,11 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp) return rates[rate_to_index(0, rates) - 1]; } +int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) +{ + return rate_to_index(rate, intel_dp->supported_rates); +} + bool intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) @@ -1374,8 +1379,7 @@ found: if (intel_dp->num_supported_rates) { intel_dp->link_bw = 0; intel_dp->rate_select = - rate_to_index(supported_rates[clock], - intel_dp->supported_rates); + intel_dp_rate_select(intel_dp, supported_rates[clock]); } else { intel_dp->link_bw = drm_dp_link_rate_to_bw_code(supported_rates[clock]); |