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| author | Zhi Wang <zhi.a.wang@intel.com> | 2015-02-10 09:11:36 (GMT) |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-02-13 22:28:22 (GMT) |
| commit | 5baa22c59f4e841eb45f8d1299043fb58370e48b (patch) | |
| tree | 8ea40a192414ce1ef8d98829db9087c37c11586d /drivers/gpu/drm/i915/intel_lrc.h | |
| parent | 25bab385a0f8e76a32a5550d696f6a17540041c5 (diff) | |
| download | linux-5baa22c59f4e841eb45f8d1299043fb58370e48b.tar.xz | |
drm/i915: Introduce bit definitions of CTXT_SR_CTRL register.
This patch introduces 2 bit definitions of context save/restore
control register.
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
Suggested-by: Dave Gordon <david.s.gordon@intel.com>
Cc: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_lrc.h')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_lrc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index 6f2d7da..ced191f 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -30,6 +30,8 @@ #define RING_ELSP(ring) ((ring)->mmio_base+0x230) #define RING_EXECLIST_STATUS(ring) ((ring)->mmio_base+0x234) #define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244) +#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3) +#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0) #define RING_CONTEXT_STATUS_BUF(ring) ((ring)->mmio_base+0x370) #define RING_CONTEXT_STATUS_PTR(ring) ((ring)->mmio_base+0x3a0) |