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| author | Rob Clark <robdclark@gmail.com> | 2013-11-30 22:51:47 (GMT) |
|---|---|---|
| committer | Rob Clark <robdclark@gmail.com> | 2014-01-09 19:44:06 (GMT) |
| commit | 06c0dd96bfbba8a9368ffd7c4b12d3bfed37001d (patch) | |
| tree | 806d07197b4fd3ab0d73885329f7de1d890f22d6 /drivers/gpu/drm/msm/msm_kms.h | |
| parent | dada25bd22a52a4351357209a8c227070cfd406d (diff) | |
| download | linux-06c0dd96bfbba8a9368ffd7c4b12d3bfed37001d.tar.xz | |
drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/msm/msm_kms.h')
| -rw-r--r-- | drivers/gpu/drm/msm/msm_kms.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h index dc0d30f..0643774 100644 --- a/drivers/gpu/drm/msm/msm_kms.h +++ b/drivers/gpu/drm/msm/msm_kms.h @@ -63,5 +63,6 @@ static inline void msm_kms_init(struct msm_kms *kms, } struct msm_kms *mdp4_kms_init(struct drm_device *dev); +struct msm_kms *mdp5_kms_init(struct drm_device *dev); #endif /* __MSM_KMS_H__ */ |