summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
diff options
context:
space:
mode:
authorVince Hsu <vinceh@nvidia.com>2014-12-22 09:11:39 (GMT)
committerBen Skeggs <bskeggs@redhat.com>2015-01-22 02:15:04 (GMT)
commit9f7fd620af29d4501ed063333824562656d46da5 (patch)
tree98583738d76273a99bdd89ccfd2adf6339839df7 /drivers/gpu/drm/nouveau/core/engine/device/nve0.c
parent47e7df39d9fb74fa11bd4b4453fc34d231b2169c (diff)
downloadlinux-9f7fd620af29d4501ed063333824562656d46da5.tar.xz
drm/nouveau/pwr: add support for GK20A
This patch adds PWR support for GK20A. But instead of adding the PWR features like firmware loading and communication with PMU firmware, we add the DVFS (Dynamic Voltage and Frequency Scaling), which is one of the PMU firmware's jobs on dGPUs, in this patch. This refers to the idle signals provided by the NVIDIA hardware and tries to adjust the performance level based on the calculated target. The reclocking policy can be fine-tuned later when we have more real use cases. Signed-off-by: Vince Hsu <vinceh@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/engine/device/nve0.c')
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nve0.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
index 7329226..d308aee 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
@@ -180,6 +180,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass;
+ device->oclass[NVDEV_SUBDEV_PWR ] = gk20a_pwr_oclass;
break;
case 0xf0:
device->cname = "GK110";