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| author | Ben Skeggs <bskeggs@redhat.com> | 2014-08-09 18:10:25 (GMT) |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2014-08-09 19:28:05 (GMT) |
| commit | 6c6ae061b61c1fd0d1823765299bcc009ddc21c8 (patch) | |
| tree | 7bf69035d788a789ae88ee900f76bfbc32b5a2d6 /drivers/gpu/drm/nouveau/nouveau_chan.c | |
| parent | bbf8906b2cad17cf9530b06db7509d0e39b02d16 (diff) | |
| download | linux-6c6ae061b61c1fd0d1823765299bcc009ddc21c8.tar.xz | |
drm/nouveau/fifo: allow direct access to channel control registers where possible
The indirect method has been left in-place here as a fallback path, as
it may not be possible to map the non-PAGE_SIZE aligned control areas
across some chipset+interface combinations.
This isn't a problem for the primary use-case where the core and drm
are linked together in kernel-land, but across a VM or (in the case
where it applies now) between the core in the kernel and a userspace
test tool.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_chan.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_chan.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index ab2d9ff..b4173be 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -291,6 +291,8 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) struct nv_dma_v0 args = {}; int ret, i; + nvif_object_map(chan->object); + /* allocate dma objects to cover all allowed vram, and gart */ if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { |