diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2012-07-19 22:17:34 (GMT) |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2012-10-03 03:12:56 (GMT) |
commit | ebb945a94bba2ce8dff7b0942ff2b3f2a52a0a69 (patch) | |
tree | 07cad59be501458e6ae1304b7c0352e322ac3387 /drivers/gpu/drm/nouveau/nv04_fbcon.c | |
parent | ac1499d9573f4aadd1d2beac11fe23af8ce90c24 (diff) | |
download | linux-ebb945a94bba2ce8dff7b0942ff2b3f2a52a0a69.tar.xz |
drm/nouveau: port all engines to new engine module format
This is a HUGE commit, but it's not nearly as bad as it looks - any problems
can be isolated to a particular chipset and engine combination. It was
simply too difficult to port each one at a time, the compat layers are
*already* ridiculous.
Most of the changes here are simply to the glue, the process for each of the
engine modules was to start with a standard skeleton and copy+paste the old
code into the appropriate places, fixing up variable names etc as needed.
v2: Marcin Slusarz <marcin.slusarz@gmail.com>
- fix find/replace bug in license header
v3: Ben Skeggs <bskeggs@redhat.com>
- bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and
left no space for kernel's requirements during GEM pushbuf submission.
- fix duplicate assignments noticed by clang
v4: Marcin Slusarz <marcin.slusarz@gmail.com>
- add sparse annotations to nv04_fifo_pause/nv04_fifo_start
- use ioread32_native/iowrite32_native for fifo control registers
v5: Ben Skeggs <bskeggs@redhat.com>
- rebase on v3.6-rc4, modified to keep copy engine fix intact
- nv10/fence: unmap fence bo before destroying
- fixed fermi regression when using nvidia gr fuc
- fixed typo in supported dma_mask checking
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv04_fbcon.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nv04_fbcon.c | 70 |
1 files changed, 36 insertions, 34 deletions
diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c index 06fb68a..35480b67 100644 --- a/drivers/gpu/drm/nouveau/nv04_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c @@ -22,19 +22,18 @@ * DEALINGS IN THE SOFTWARE. */ -#include "drmP.h" -#include "nouveau_drv.h" +#include <core/object.h> + +#include "nouveau_drm.h" #include "nouveau_dma.h" -#include <core/ramht.h> #include "nouveau_fbcon.h" int nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) { struct nouveau_fbdev *nfbdev = info->par; - struct drm_device *dev = nfbdev->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_channel *chan = dev_priv->channel; + struct nouveau_drm *drm = nouveau_newpriv(nfbdev->dev); + struct nouveau_channel *chan = drm->channel; int ret; ret = RING_SPACE(chan, 4); @@ -53,9 +52,8 @@ int nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) { struct nouveau_fbdev *nfbdev = info->par; - struct drm_device *dev = nfbdev->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_channel *chan = dev_priv->channel; + struct nouveau_drm *drm = nouveau_newpriv(nfbdev->dev); + struct nouveau_channel *chan = drm->channel; int ret; ret = RING_SPACE(chan, 7); @@ -81,9 +79,8 @@ int nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) { struct nouveau_fbdev *nfbdev = info->par; - struct drm_device *dev = nfbdev->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_channel *chan = dev_priv->channel; + struct nouveau_drm *drm = nouveau_newpriv(nfbdev->dev); + struct nouveau_channel *chan = drm->channel; uint32_t fg; uint32_t bg; uint32_t dsize; @@ -142,9 +139,10 @@ nv04_fbcon_accel_init(struct fb_info *info) { struct nouveau_fbdev *nfbdev = info->par; struct drm_device *dev = nfbdev->dev; - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_channel *chan = dev_priv->channel; - const int sub = NvSubCtxSurf2D; + struct nouveau_drm *drm = nouveau_newpriv(dev); + struct nouveau_channel *chan = drm->channel; + struct nouveau_device *device = nv_device(drm->device); + struct nouveau_object *object; int surface_fmt, pattern_fmt, rect_fmt; int ret; @@ -176,31 +174,35 @@ nv04_fbcon_accel_init(struct fb_info *info) return -EINVAL; } - ret = nouveau_gpuobj_gr_new(chan, NvCtxSurf2D, - dev_priv->card_type >= NV_10 ? - 0x0062 : 0x0042); + ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvCtxSurf2D, + device->card_type >= NV_10 ? 0x0062 : 0x0042, + NULL, 0, &object); if (ret) return ret; - ret = nouveau_gpuobj_gr_new(chan, NvClipRect, 0x0019); + ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvClipRect, + 0x0019, NULL, 0, &object); if (ret) return ret; - ret = nouveau_gpuobj_gr_new(chan, NvRop, 0x0043); + ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvRop, + 0x0043, NULL, 0, &object); if (ret) return ret; - ret = nouveau_gpuobj_gr_new(chan, NvImagePatt, 0x0044); + ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvImagePatt, + 0x0044, NULL, 0, &object); if (ret) return ret; - ret = nouveau_gpuobj_gr_new(chan, NvGdiRect, 0x004a); + ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvGdiRect, + 0x004a, NULL, 0, &object); if (ret) return ret; - ret = nouveau_gpuobj_gr_new(chan, NvImageBlit, - dev_priv->chipset >= 0x11 ? - 0x009f : 0x005f); + ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvImageBlit, + device->chipset >= 0x11 ? 0x009f : 0x005f, + NULL, 0, &object); if (ret) return ret; @@ -209,25 +211,25 @@ nv04_fbcon_accel_init(struct fb_info *info) return 0; } - BEGIN_NV04(chan, sub, 0x0000, 1); + BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); OUT_RING(chan, NvCtxSurf2D); - BEGIN_NV04(chan, sub, 0x0184, 2); + BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0184, 2); OUT_RING(chan, NvDmaFB); OUT_RING(chan, NvDmaFB); - BEGIN_NV04(chan, sub, 0x0300, 4); + BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 4); OUT_RING(chan, surface_fmt); OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16)); OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base); OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base); - BEGIN_NV04(chan, sub, 0x0000, 1); + BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); OUT_RING(chan, NvRop); - BEGIN_NV04(chan, sub, 0x0300, 1); + BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 1); OUT_RING(chan, 0x55); - BEGIN_NV04(chan, sub, 0x0000, 1); + BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); OUT_RING(chan, NvImagePatt); - BEGIN_NV04(chan, sub, 0x0300, 8); + BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 8); OUT_RING(chan, pattern_fmt); #ifdef __BIG_ENDIAN OUT_RING(chan, 2); @@ -241,9 +243,9 @@ nv04_fbcon_accel_init(struct fb_info *info) OUT_RING(chan, ~0); OUT_RING(chan, ~0); - BEGIN_NV04(chan, sub, 0x0000, 1); + BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); OUT_RING(chan, NvClipRect); - BEGIN_NV04(chan, sub, 0x0300, 2); + BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 2); OUT_RING(chan, 0); OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual); |