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authorBen Skeggs <bskeggs@redhat.com>2015-08-20 04:54:17 (GMT)
committerBen Skeggs <bskeggs@redhat.com>2015-08-28 02:40:37 (GMT)
commit1d2a1e53865266a67fb569705eba3ec992682721 (patch)
tree9ee9f3817de71fe0a39f0d27ddcc80dcd2179b2b /drivers/gpu/drm/nouveau/nvkm/engine/fifo
parentf027f49166171c98d5945af12ac3ee9bc9f9bf4c (diff)
downloadlinux-1d2a1e53865266a67fb569705eba3ec992682721.tar.xz
drm/nouveau/ramht: remove dependence on namedb
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/fifo')
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c12
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c4
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c4
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c14
5 files changed, 20 insertions, 16 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
index 058296b..2997193 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
@@ -161,7 +161,7 @@ g84_fifo_object_attach(struct nvkm_object *parent,
}
}
- return nvkm_ramht_insert(chan->ramht, 0, handle, context);
+ return nvkm_ramht_insert(chan->ramht, NULL, 0, 0, handle, context);
}
static int
@@ -172,6 +172,7 @@ g84_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine,
union {
struct nv50_channel_dma_v0 v0;
} *args = data;
+ struct nvkm_device *device = parent->engine->subdev.device;
struct nv50_fifo_base *base = (void *)parent;
struct nv50_fifo_chan *chan;
int ret;
@@ -208,7 +209,7 @@ g84_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine,
args->v0.chid = chan->base.chid;
- ret = nvkm_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
+ ret = nvkm_ramht_new(device, 0x8000, 16, &base->base.gpuobj,
&chan->ramht);
if (ret)
return ret;
@@ -232,7 +233,7 @@ g84_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine,
nvkm_wo32(base->ramfc, 0x7c, 0x30000001);
nvkm_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
(4 << 24) /* SEARCH_FULL */ |
- (chan->ramht->gpuobj.node->offset >> 4));
+ (chan->ramht->gpuobj->node->offset >> 4));
nvkm_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
nvkm_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
nvkm_done(base->ramfc);
@@ -247,6 +248,7 @@ g84_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine,
union {
struct nv50_channel_gpfifo_v0 v0;
} *args = data;
+ struct nvkm_device *device = parent->engine->subdev.device;
struct nv50_fifo_base *base = (void *)parent;
struct nv50_fifo_chan *chan;
u64 ioffset, ilength;
@@ -285,7 +287,7 @@ g84_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine,
args->v0.chid = chan->base.chid;
- ret = nvkm_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
+ ret = nvkm_ramht_new(device, 0x8000, 16, &base->base.gpuobj,
&chan->ramht);
if (ret)
return ret;
@@ -309,7 +311,7 @@ g84_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine,
nvkm_wo32(base->ramfc, 0x7c, 0x30000001);
nvkm_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
(4 << 24) /* SEARCH_FULL */ |
- (chan->ramht->gpuobj.node->offset >> 4));
+ (chan->ramht->gpuobj->node->offset >> 4));
nvkm_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
nvkm_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
nvkm_done(base->ramfc);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
index 4bec707..cd50093 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
@@ -86,7 +86,7 @@ nv04_fifo_object_attach(struct nvkm_object *parent,
context |= chid << 24;
mutex_lock(&nv_subdev(fifo)->mutex);
- ret = nvkm_ramht_insert(imem->ramht, chid, handle, context);
+ ret = nvkm_ramht_insert(imem->ramht, NULL, chid, 0, handle, context);
mutex_unlock(&nv_subdev(fifo)->mutex);
return ret;
}
@@ -625,7 +625,7 @@ nv04_fifo_init(struct nvkm_object *object)
nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
((ramht->bits - 9) << 16) |
- (ramht->gpuobj.addr >> 8));
+ (ramht->gpuobj->addr >> 8));
nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8);
nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c
index 69b9d42..e271804 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c
@@ -191,7 +191,7 @@ nv17_fifo_init(struct nvkm_object *object)
nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
((ramht->bits - 9) << 16) |
- (ramht->gpuobj.addr >> 8));
+ (ramht->gpuobj->addr >> 8));
nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8);
nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8 |
0x00010000);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
index a2d8da8..f2f0e3d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
@@ -98,7 +98,7 @@ nv40_fifo_object_attach(struct nvkm_object *parent,
context |= chid << 23;
mutex_lock(&nv_subdev(fifo)->mutex);
- ret = nvkm_ramht_insert(imem->ramht, chid, handle, context);
+ ret = nvkm_ramht_insert(imem->ramht, NULL, chid, 0, handle, context);
mutex_unlock(&nv_subdev(fifo)->mutex);
return ret;
}
@@ -322,7 +322,7 @@ nv40_fifo_init(struct nvkm_object *object)
nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
((ramht->bits - 9) << 16) |
- (ramht->gpuobj.addr >> 8));
+ (ramht->gpuobj->addr >> 8));
nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8);
switch (nv_device(fifo)->chipset) {
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
index 620c0cf..2b37fda 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
@@ -182,7 +182,7 @@ nv50_fifo_object_attach(struct nvkm_object *parent,
}
}
- return nvkm_ramht_insert(chan->ramht, 0, handle, context);
+ return nvkm_ramht_insert(chan->ramht, NULL, 0, 0, handle, context);
}
void
@@ -200,6 +200,7 @@ nv50_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine,
union {
struct nv50_channel_dma_v0 v0;
} *args = data;
+ struct nvkm_device *device = parent->engine->subdev.device;
struct nv50_fifo_base *base = (void *)parent;
struct nv50_fifo_chan *chan;
int ret;
@@ -231,7 +232,7 @@ nv50_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine,
nv_parent(chan)->object_attach = nv50_fifo_object_attach;
nv_parent(chan)->object_detach = nv50_fifo_object_detach;
- ret = nvkm_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
+ ret = nvkm_ramht_new(device, 0x8000, 16, &base->base.gpuobj,
&chan->ramht);
if (ret)
return ret;
@@ -250,7 +251,7 @@ nv50_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine,
nvkm_wo32(base->ramfc, 0x7c, 0x30000001);
nvkm_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
(4 << 24) /* SEARCH_FULL */ |
- (chan->ramht->gpuobj.node->offset >> 4));
+ (chan->ramht->gpuobj->node->offset >> 4));
nvkm_done(base->ramfc);
return 0;
}
@@ -263,6 +264,7 @@ nv50_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine,
union {
struct nv50_channel_gpfifo_v0 v0;
} *args = data;
+ struct nvkm_device *device = parent->engine->subdev.device;
struct nv50_fifo_base *base = (void *)parent;
struct nv50_fifo_chan *chan;
u64 ioffset, ilength;
@@ -296,7 +298,7 @@ nv50_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine,
nv_parent(chan)->object_attach = nv50_fifo_object_attach;
nv_parent(chan)->object_detach = nv50_fifo_object_detach;
- ret = nvkm_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
+ ret = nvkm_ramht_new(device, 0x8000, 16, &base->base.gpuobj,
&chan->ramht);
if (ret)
return ret;
@@ -315,7 +317,7 @@ nv50_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine,
nvkm_wo32(base->ramfc, 0x7c, 0x30000001);
nvkm_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
(4 << 24) /* SEARCH_FULL */ |
- (chan->ramht->gpuobj.node->offset >> 4));
+ (chan->ramht->gpuobj->node->offset >> 4));
nvkm_done(base->ramfc);
return 0;
}
@@ -324,7 +326,7 @@ void
nv50_fifo_chan_dtor(struct nvkm_object *object)
{
struct nv50_fifo_chan *chan = (void *)object;
- nvkm_ramht_ref(NULL, &chan->ramht);
+ nvkm_ramht_del(&chan->ramht);
nvkm_fifo_channel_destroy(&chan->base);
}