drm/nouveau/msppp: rename from ppp (no binary change)

Switch to NVIDIA's name for the device.

The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

3 files changed, 18 insertions, 18 deletions

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
index 4a3638e..6abcd5c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
@@ -58,7 +58,7 @@ nv84_fifo_context_attach(struct nouveau_object *parent,
 	case NVDEV_ENGINE_SW    : return 0;
 	case NVDEV_ENGINE_GR    : addr = 0x0020; break;
 	case NVDEV_ENGINE_VP    : addr = 0x0040; break;
-	case NVDEV_ENGINE_PPP   :
+	case NVDEV_ENGINE_MSPPP :
 	case NVDEV_ENGINE_MPEG  : addr = 0x0060; break;
 	case NVDEV_ENGINE_BSP   :
 	case NVDEV_ENGINE_MSVLD : addr = 0x0080; break;
@@ -96,7 +96,7 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
 	case NVDEV_ENGINE_SW    : return 0;
 	case NVDEV_ENGINE_GR    : engn = 0; addr = 0x0020; break;
 	case NVDEV_ENGINE_VP    : engn = 3; addr = 0x0040; break;
-	case NVDEV_ENGINE_PPP   :
+	case NVDEV_ENGINE_MSPPP :
 	case NVDEV_ENGINE_MPEG  : engn = 1; addr = 0x0060; break;
 	case NVDEV_ENGINE_BSP   :
 	case NVDEV_ENGINE_MSVLD : engn = 5; addr = 0x0080; break;
@@ -145,7 +145,7 @@ nv84_fifo_object_attach(struct nouveau_object *parent,
 	case NVDEV_ENGINE_SW    : context |= 0x00000000; break;
 	case NVDEV_ENGINE_GR    : context |= 0x00100000; break;
 	case NVDEV_ENGINE_MPEG  :
-	case NVDEV_ENGINE_PPP   : context |= 0x00200000; break;
+	case NVDEV_ENGINE_MSPPP : context |= 0x00200000; break;
 	case NVDEV_ENGINE_ME    :
 	case NVDEV_ENGINE_CE0   : context |= 0x00300000; break;
 	case NVDEV_ENGINE_VP    : context |= 0x00400000; break;
@@ -195,7 +195,7 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
 					  (1ULL << NVDEV_ENGINE_SEC) |
 					  (1ULL << NVDEV_ENGINE_BSP) |
 					  (1ULL << NVDEV_ENGINE_MSVLD) |
-					  (1ULL << NVDEV_ENGINE_PPP) |
+					  (1ULL << NVDEV_ENGINE_MSPPP) |
 					  (1ULL << NVDEV_ENGINE_CE0) |
 					  (1ULL << NVDEV_ENGINE_VIC), &chan);
 	*pobject = nv_object(chan);
@@ -270,7 +270,7 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
 					  (1ULL << NVDEV_ENGINE_SEC) |
 					  (1ULL << NVDEV_ENGINE_BSP) |
 					  (1ULL << NVDEV_ENGINE_MSVLD) |
-					  (1ULL << NVDEV_ENGINE_PPP) |
+					  (1ULL << NVDEV_ENGINE_MSPPP) |
 					  (1ULL << NVDEV_ENGINE_CE0) |
 					  (1ULL << NVDEV_ENGINE_VIC), &chan);
 	*pobject = nv_object(chan);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
index 1511e38..d86601c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
@@ -126,7 +126,7 @@ nvc0_fifo_context_attach(struct nouveau_object *parent,
 	case NVDEV_ENGINE_CE1  : addr = 0x0240; break;
 	case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
 	case NVDEV_ENGINE_VP   : addr = 0x0250; break;
-	case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
+	case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
 	default:
 		return -EINVAL;
 	}
@@ -163,7 +163,7 @@ nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
 	case NVDEV_ENGINE_CE1  : addr = 0x0240; break;
 	case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
 	case NVDEV_ENGINE_VP   : addr = 0x0250; break;
-	case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
+	case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
 	default:
 		return -EINVAL;
 	}
@@ -216,7 +216,7 @@ nvc0_fifo_chan_ctor(struct nouveau_object *parent,
 					  (1ULL << NVDEV_ENGINE_CE1) |
 					  (1ULL << NVDEV_ENGINE_MSVLD) |
 					  (1ULL << NVDEV_ENGINE_VP) |
-					  (1ULL << NVDEV_ENGINE_PPP), &chan);
+					  (1ULL << NVDEV_ENGINE_MSPPP), &chan);
 	*pobject = nv_object(chan);
 	if (ret)
 		return ret;
@@ -383,7 +383,7 @@ nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn)
 	switch (engn) {
 	case NVDEV_ENGINE_GR   : engn = 0; break;
 	case NVDEV_ENGINE_MSVLD: engn = 1; break;
-	case NVDEV_ENGINE_PPP  : engn = 2; break;
+	case NVDEV_ENGINE_MSPPP: engn = 2; break;
 	case NVDEV_ENGINE_VP   : engn = 3; break;
 	case NVDEV_ENGINE_CE0  : engn = 4; break;
 	case NVDEV_ENGINE_CE1  : engn = 5; break;
@@ -400,7 +400,7 @@ nvc0_fifo_engine(struct nvc0_fifo_priv *priv, u32 engn)
 	switch (engn) {
 	case 0: engn = NVDEV_ENGINE_GR; break;
 	case 1: engn = NVDEV_ENGINE_MSVLD; break;
-	case 2: engn = NVDEV_ENGINE_PPP; break;
+	case 2: engn = NVDEV_ENGINE_MSPPP; break;
 	case 3: engn = NVDEV_ENGINE_VP; break;
 	case 4: engn = NVDEV_ENGINE_CE0; break;
 	case 5: engn = NVDEV_ENGINE_CE1; break;
@@ -549,7 +549,7 @@ nvc0_fifo_fault_engine[] = {
 	{ 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM },
 	{ 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO },
 	{ 0x10, "PMSVLD", NULL, NVDEV_ENGINE_MSVLD },
-	{ 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP },
+	{ 0x11, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP },
 	{ 0x13, "PCOUNTER" },
 	{ 0x14, "PVP", NULL, NVDEV_ENGINE_VP },
 	{ 0x15, "PCE0", NULL, NVDEV_ENGINE_CE0 },
@@ -582,7 +582,7 @@ nvc0_fifo_fault_hubclient[] = {
 	{ 0x07, "BAR_READ" },
 	{ 0x08, "BAR_WRITE" },
 	{ 0x0b, "PVP" },
-	{ 0x0c, "PPPP" },
+	{ 0x0c, "PMSPPP" },
 	{ 0x0d, "PMSVLD" },
 	{ 0x11, "PCOUNTER" },
 	{ 0x12, "PDAEMON" },
@@ -940,7 +940,7 @@ nvc0_fifo_init(struct nouveau_object *object)
 	if (priv->spoon_nr >= 3) {
 		nv_wr32(priv, 0x002208, ~(1 << 0)); /* PGRAPH */
 		nv_wr32(priv, 0x00220c, ~(1 << 1)); /* PVP */
-		nv_wr32(priv, 0x002210, ~(1 << 1)); /* PPP */
+		nv_wr32(priv, 0x002210, ~(1 << 1)); /* PMSPP */
 		nv_wr32(priv, 0x002214, ~(1 << 1)); /* PMSVLD */
 		nv_wr32(priv, 0x002218, ~(1 << 2)); /* PCE0 */
 		nv_wr32(priv, 0x00221c, ~(1 << 1)); /* PCE1 */
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
index 324008e..81dc280 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
@@ -49,7 +49,7 @@ static const struct {
 	_(NVDEV_ENGINE_GR      , (1ULL << NVDEV_ENGINE_SW) |
 				 (1ULL << NVDEV_ENGINE_CE2)),
 	_(NVDEV_ENGINE_VP      , 0),
-	_(NVDEV_ENGINE_PPP     , 0),
+	_(NVDEV_ENGINE_MSPPP   , 0),
 	_(NVDEV_ENGINE_MSVLD   , 0),
 	_(NVDEV_ENGINE_CE0     , 0),
 	_(NVDEV_ENGINE_CE1     , 0),
@@ -151,7 +151,7 @@ nve0_fifo_context_attach(struct nouveau_object *parent,
 	case NVDEV_ENGINE_GR   : addr = 0x0210; break;
 	case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
 	case NVDEV_ENGINE_VP   : addr = 0x0250; break;
-	case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
+	case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
 	default:
 		return -EINVAL;
 	}
@@ -189,7 +189,7 @@ nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
 	case NVDEV_ENGINE_GR   : addr = 0x0210; break;
 	case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
 	case NVDEV_ENGINE_VP   : addr = 0x0250; break;
-	case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
+	case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
 	default:
 		return -EINVAL;
 	}
@@ -417,7 +417,7 @@ nve0_fifo_engidx(struct nve0_fifo_priv *priv, u32 engn)
 	case NVDEV_ENGINE_GR   :
 	case NVDEV_ENGINE_CE2  : engn = 0; break;
 	case NVDEV_ENGINE_MSVLD: engn = 1; break;
-	case NVDEV_ENGINE_PPP  : engn = 2; break;
+	case NVDEV_ENGINE_MSPPP: engn = 2; break;
 	case NVDEV_ENGINE_VP   : engn = 3; break;
 	case NVDEV_ENGINE_CE0  : engn = 4; break;
 	case NVDEV_ENGINE_CE1  : engn = 5; break;
@@ -620,7 +620,7 @@ nve0_fifo_fault_engine[] = {
 	{ 0x08, "PBDMA1", NULL, NVDEV_ENGINE_FIFO },
 	{ 0x09, "PBDMA2", NULL, NVDEV_ENGINE_FIFO },
 	{ 0x10, "MSVLD", NULL, NVDEV_ENGINE_MSVLD },
-	{ 0x11, "MSPPP", NULL, NVDEV_ENGINE_PPP },
+	{ 0x11, "MSPPP", NULL, NVDEV_ENGINE_MSPPP },
 	{ 0x13, "PERF" },
 	{ 0x14, "MSPDEC", NULL, NVDEV_ENGINE_VP },
 	{ 0x15, "CE0", NULL, NVDEV_ENGINE_CE0 },