diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2015-08-20 04:54:13 (GMT) |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2015-08-28 02:40:27 (GMT) |
commit | 9ccdc76006e3b6ca46c8dbc446bc2e3f6d8d95cb (patch) | |
tree | 0fae14e906a8fd904aedd5ccba0f2357f88bfd20 /drivers/gpu/drm/nouveau | |
parent | 63902181a7ce9177c476103694cbdf45ee5c0578 (diff) | |
download | linux-9ccdc76006e3b6ca46c8dbc446bc2e3f6d8d95cb.tar.xz |
drm/nouveau/xtensa: remove object accessor functions
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau')
-rw-r--r-- | drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c | 58 |
4 files changed, 24 insertions, 40 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h index bfe49b6..5bd4b6e 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h @@ -30,6 +30,4 @@ int nvkm_xtensa_create_(struct nvkm_object *, #define _nvkm_xtensa_dtor _nvkm_engine_dtor int _nvkm_xtensa_init(struct nvkm_object *); int _nvkm_xtensa_fini(struct nvkm_object *, bool); -u32 _nvkm_xtensa_rd32(struct nvkm_object *, u64); -void _nvkm_xtensa_wr32(struct nvkm_object *, u64, u32); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c index 6b69d66..0f140bc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c @@ -87,7 +87,5 @@ g84_bsp_oclass = { .dtor = _nvkm_xtensa_dtor, .init = _nvkm_xtensa_init, .fini = _nvkm_xtensa_fini, - .rd32 = _nvkm_xtensa_rd32, - .wr32 = _nvkm_xtensa_wr32, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c index 703ddcf..a4ff78a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c @@ -87,7 +87,5 @@ g84_vp_oclass = { .dtor = _nvkm_xtensa_dtor, .init = _nvkm_xtensa_init, .fini = _nvkm_xtensa_fini, - .rd32 = _nvkm_xtensa_rd32, - .wr32 = _nvkm_xtensa_wr32, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c index 027660c..dd5cef1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c @@ -23,20 +23,6 @@ #include <core/engctx.h> -u32 -_nvkm_xtensa_rd32(struct nvkm_object *object, u64 addr) -{ - struct nvkm_xtensa *xtensa = (void *)object; - return nvkm_rd32(xtensa->engine.subdev.device, xtensa->addr + addr); -} - -void -_nvkm_xtensa_wr32(struct nvkm_object *object, u64 addr, u32 data) -{ - struct nvkm_xtensa *xtensa = (void *)object; - nvkm_wr32(xtensa->engine.subdev.device, xtensa->addr + addr, data); -} - int _nvkm_xtensa_engctx_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -56,15 +42,16 @@ _nvkm_xtensa_intr(struct nvkm_subdev *subdev) { struct nvkm_xtensa *xtensa = (void *)subdev; struct nvkm_device *device = xtensa->engine.subdev.device; - u32 unk104 = nv_ro32(xtensa, 0xd04); - u32 intr = nv_ro32(xtensa, 0xc20); - u32 chan = nv_ro32(xtensa, 0xc28); - u32 unk10c = nv_ro32(xtensa, 0xd0c); + const u32 base = xtensa->addr; + u32 unk104 = nvkm_rd32(device, base + 0xd04); + u32 intr = nvkm_rd32(device, base + 0xc20); + u32 chan = nvkm_rd32(device, base + 0xc28); + u32 unk10c = nvkm_rd32(device, base + 0xd0c); if (intr & 0x10) nvkm_warn(subdev, "Watchdog interrupt, engine hung.\n"); - nv_wo32(xtensa, 0xc20, intr); - intr = nv_ro32(xtensa, 0xc20); + nvkm_wr32(device, base + 0xc20, intr); + intr = nvkm_rd32(device, base + 0xc20); if (unk104 == 0x10001 && unk10c == 0x200 && chan && !intr) { nvkm_debug(subdev, "Enabling FIFO_CTRL\n"); nvkm_mask(device, xtensa->addr + 0xd94, 0, xtensa->fifo_val); @@ -97,6 +84,7 @@ _nvkm_xtensa_init(struct nvkm_object *object) struct nvkm_xtensa *xtensa = (void *)object; struct nvkm_subdev *subdev = &xtensa->engine.subdev; struct nvkm_device *device = subdev->device; + const u32 base = xtensa->addr; const struct firmware *fw; char name[32]; int i, ret; @@ -137,24 +125,24 @@ _nvkm_xtensa_init(struct nvkm_object *object) release_firmware(fw); } - nv_wo32(xtensa, 0xd10, 0x1fffffff); /* ?? */ - nv_wo32(xtensa, 0xd08, 0x0fffffff); /* ?? */ + nvkm_wr32(device, base + 0xd10, 0x1fffffff); /* ?? */ + nvkm_wr32(device, base + 0xd08, 0x0fffffff); /* ?? */ - nv_wo32(xtensa, 0xd28, xtensa->unkd28); /* ?? */ - nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */ - nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */ + nvkm_wr32(device, base + 0xd28, xtensa->unkd28); /* ?? */ + nvkm_wr32(device, base + 0xc20, 0x3f); /* INTR */ + nvkm_wr32(device, base + 0xd84, 0x3f); /* INTR_EN */ - nv_wo32(xtensa, 0xcc0, xtensa->gpu_fw->addr >> 8); /* XT_REGION_BASE */ - nv_wo32(xtensa, 0xcc4, 0x1c); /* XT_REGION_SETUP */ - nv_wo32(xtensa, 0xcc8, xtensa->gpu_fw->size >> 8); /* XT_REGION_LIMIT */ + nvkm_wr32(device, base + 0xcc0, xtensa->gpu_fw->addr >> 8); /* XT_REGION_BASE */ + nvkm_wr32(device, base + 0xcc4, 0x1c); /* XT_REGION_SETUP */ + nvkm_wr32(device, base + 0xcc8, xtensa->gpu_fw->size >> 8); /* XT_REGION_LIMIT */ tmp = nvkm_rd32(device, 0x0); - nv_wo32(xtensa, 0xde0, tmp); /* SCRATCH_H2X */ + nvkm_wr32(device, base + 0xde0, tmp); /* SCRATCH_H2X */ - nv_wo32(xtensa, 0xce8, 0xf); /* XT_REGION_SETUP */ + nvkm_wr32(device, base + 0xce8, 0xf); /* XT_REGION_SETUP */ - nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */ - nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */ + nvkm_wr32(device, base + 0xc20, 0x3f); /* INTR */ + nvkm_wr32(device, base + 0xd84, 0x3f); /* INTR_EN */ return 0; } @@ -162,9 +150,11 @@ int _nvkm_xtensa_fini(struct nvkm_object *object, bool suspend) { struct nvkm_xtensa *xtensa = (void *)object; + struct nvkm_device *device = xtensa->engine.subdev.device; + const u32 base = xtensa->addr; - nv_wo32(xtensa, 0xd84, 0); /* INTR_EN */ - nv_wo32(xtensa, 0xd94, 0); /* FIFO_CTRL */ + nvkm_wr32(device, base + 0xd84, 0); /* INTR_EN */ + nvkm_wr32(device, base + 0xd94, 0); /* FIFO_CTRL */ if (!suspend) nvkm_gpuobj_ref(NULL, &xtensa->gpu_fw); |