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authorAlex Deucher <alexander.deucher@amd.com>2012-07-17 18:02:31 (GMT)
committerChristian König <deathsimple@vodafone.de>2012-07-18 11:53:17 (GMT)
commit89d35807fb0fe53b84e88e759cc39107a6195e5f (patch)
treeafb2e2cb9439239e6f83ad339ad624f42d012adc /drivers/gpu/drm/radeon/si.c
parent8b25ed3482885e5f1dc65ace796e90f879d76c52 (diff)
downloadlinux-89d35807fb0fe53b84e88e759cc39107a6195e5f.tar.xz
drm/radeon: update rptr saving logic for memory buffers
Add support for using memory buffers rather than scratch registers. Some rings may not be able to write to scratch registers. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/si.c')
-rw-r--r--drivers/gpu/drm/radeon/si.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 2b12cae..7c3e330 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1772,12 +1772,20 @@ void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
} else {
+ u32 next_rptr;
if (ring->rptr_save_reg) {
- uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
+ next_rptr = ring->wptr + 3 + 4 + 8;
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
radeon_ring_write(ring, ((ring->rptr_save_reg -
PACKET3_SET_CONFIG_REG_START) >> 2));
radeon_ring_write(ring, next_rptr);
+ } else if (rdev->wb.enabled) {
+ next_rptr = ring->wptr + 5 + 4 + 8;
+ radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+ radeon_ring_write(ring, (1 << 8));
+ radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
+ radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
+ radeon_ring_write(ring, next_rptr);
}
header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);