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authorThierry Reding <treding@nvidia.com>2014-12-02 14:12:28 (GMT)
committerThierry Reding <treding@nvidia.com>2015-01-27 09:14:46 (GMT)
commitd5bae6f33ee98cf4c6939c4b8db2fc76c1eed720 (patch)
tree4e978d540c6b4af8501f9f03f79c1c0909aaa271 /drivers/gpu/drm/tegra/dc.c
parent132085d84fca65c46b56dc0f8233910906a15e8d (diff)
downloadlinux-d5bae6f33ee98cf4c6939c4b8db2fc76c1eed720.tar.xz
drm/tegra: output: Make ->setup_clock() optional
In order to transition output drivers to using the struct tegra_output as a helper rather than midlayer, make this callback optional. Instead drivers should implement the equivalent as part of ->mode_fixup(). For the conversion to atomic modesetting a new callback ->atomic_check() should be implemented that updates the display controller's state with the corresponding parent clock, rate and shift clock divider. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/dc.c')
-rw-r--r--drivers/gpu/drm/tegra/dc.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index d511730..e35e107 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -1067,10 +1067,18 @@ static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
return -ENODEV;
/*
+ * The ->setup_clock() callback is optional, but if encoders don't
+ * implement it they most likely need to do the equivalent within the
+ * ->mode_fixup() callback.
+ */
+ if (!output->ops || !output->ops->setup_clock)
+ return 0;
+
+ /*
* This assumes that the parent clock is pll_d_out0 or pll_d2_out
* respectively, each of which divides the base pll_d by 2.
*/
- err = tegra_output_setup_clock(output, dc->clk, pclk, &div);
+ err = output->ops->setup_clock(output, dc->clk, pclk, &div);
if (err < 0) {
dev_err(dc->dev, "failed to setup clock: %ld\n", err);
return err;