drm/nouveau/core: have fifo store a unique context identifier at attach time

This value will match something that's easily available from the engine IRQ
handlers, and used to lookup the relevant context.

Since the changes in how this is done on each generation match when the
major PFIFO changes happened, fifo is responsible for calculating the
correct value to avoid duplicating the same code among many engine modules.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

11 files changed, 23 insertions, 2 deletions

diff --git a/drivers/gpu/drm/nouveau/core/core/engctx.c b/drivers/gpu/drm/nouveau/core/core/engctx.c
index 38c0612..ad4bbe1 100644
--- a/drivers/gpu/drm/nouveau/core/core/engctx.c
+++ b/drivers/gpu/drm/nouveau/core/core/engctx.c
@@ -105,6 +105,7 @@ nouveau_engctx_create_(struct nouveau_object *parent,
 	if (client->vm)
 		atomic_inc(&client->vm->engref[nv_engidx(engobj)]);
 	list_add(&nv_engctx(engctx)->head, &engine->contexts);
+	nv_engctx(engctx)->addr = ~0ULL;
 	spin_unlock_irqrestore(&engine->lock, save);
 	return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
index 8b7513f..7cd5d76 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
@@ -102,6 +102,14 @@ nv04_fifo_object_detach(struct nouveau_object *parent, int cookie)
 	mutex_unlock(&nv_subdev(priv)->mutex);
 }
 
+int
+nv04_fifo_context_attach(struct nouveau_object *parent,
+			 struct nouveau_object *object)
+{
+	nv_engctx(object)->addr = nouveau_fifo_chan(parent)->chid;
+	return 0;
+}
+
 static int
 nv04_fifo_chan_ctor(struct nouveau_object *parent,
 		    struct nouveau_object *engine,
@@ -127,6 +135,7 @@ nv04_fifo_chan_ctor(struct nouveau_object *parent,
 
 	nv_parent(chan)->object_attach = nv04_fifo_object_attach;
 	nv_parent(chan)->object_detach = nv04_fifo_object_detach;
+	nv_parent(chan)->context_attach = nv04_fifo_context_attach;
 	chan->ramfc = chan->base.chid * 32;
 
 	nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset);
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c
index 391fefa..5d3638b 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c
@@ -78,6 +78,7 @@ nv10_fifo_chan_ctor(struct nouveau_object *parent,
 
 	nv_parent(chan)->object_attach = nv04_fifo_object_attach;
 	nv_parent(chan)->object_detach = nv04_fifo_object_detach;
+	nv_parent(chan)->context_attach = nv04_fifo_context_attach;
 	chan->ramfc = chan->base.chid * 32;
 
 	nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset);
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c
index 3b9d6c9..f223eb9 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c
@@ -85,6 +85,7 @@ nv17_fifo_chan_ctor(struct nouveau_object *parent,
 
 	nv_parent(chan)->object_attach = nv04_fifo_object_attach;
 	nv_parent(chan)->object_detach = nv04_fifo_object_detach;
+	nv_parent(chan)->context_attach = nv04_fifo_context_attach;
 	chan->ramfc = chan->base.chid * 64;
 
 	nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset);
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
index 43d5c9e..ce97c5e 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
@@ -128,11 +128,12 @@ nv40_fifo_context_attach(struct nouveau_object *parent,
 	}
 
 	spin_lock_irqsave(&priv->base.lock, flags);
+	nv_engctx(engctx)->addr = nv_gpuobj(engctx)->addr >> 4;
 	nv_mask(priv, 0x002500, 0x00000001, 0x00000000);
 
 	if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid)
-		nv_wr32(priv, reg, nv_gpuobj(engctx)->addr >> 4);
-	nv_wo32(priv->ramfc, chan->ramfc + ctx, nv_gpuobj(engctx)->addr >> 4);
+		nv_wr32(priv, reg, nv_engctx(engctx)->addr);
+	nv_wo32(priv->ramfc, chan->ramfc + ctx, nv_engctx(engctx)->addr);
 
 	nv_mask(priv, 0x002500, 0x00000001, 0x00000001);
 	spin_unlock_irqrestore(&priv->base.lock, flags);
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
index 5b80f3e..452f224 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
@@ -81,6 +81,7 @@ nv50_fifo_context_attach(struct nouveau_object *parent,
 		return -EINVAL;
 	}
 
+	nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
 	nv_wo32(base->eng, addr + 0x00, 0x00190000);
 	nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit));
 	nv_wo32(base->eng, addr + 0x08, lower_32_bits(start));
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
index 694a9bb..80c3927 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
@@ -62,6 +62,7 @@ nv84_fifo_context_attach(struct nouveau_object *parent,
 		return -EINVAL;
 	}
 
+	nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
 	nv_wo32(base->eng, addr + 0x00, 0x00190000);
 	nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit));
 	nv_wo32(base->eng, addr + 0x08, lower_32_bits(start));
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
index a4ae2bf..d10dca2 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
@@ -112,6 +112,8 @@ nvc0_fifo_context_attach(struct nouveau_object *parent,
 					    NV_MEM_ACCESS_RW, &ectx->vma);
 		if (ret)
 			return ret;
+
+		nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
 	}
 
 	nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
index c3f4955..042afad 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
@@ -147,6 +147,8 @@ nve0_fifo_context_attach(struct nouveau_object *parent,
 					    NV_MEM_ACCESS_RW, &ectx->vma);
 		if (ret)
 			return ret;
+
+		nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
 	}
 
 	nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);
diff --git a/drivers/gpu/drm/nouveau/core/include/core/engctx.h b/drivers/gpu/drm/nouveau/core/include/core/engctx.h
index 3bc6ccd..227b2c1 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/engctx.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/engctx.h
@@ -13,6 +13,7 @@ struct nouveau_engctx {
 	struct nouveau_gpuobj base;
 	struct nouveau_vma vma;
 	struct list_head head;
+	u64 addr;
 };
 
 static inline struct nouveau_engctx *
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
index f213387..d67fed1 100644
--- a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
+++ b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
@@ -106,5 +106,6 @@ extern struct nouveau_oclass nvc0_fifo_oclass;
 extern struct nouveau_oclass nve0_fifo_oclass;
 
 void nv04_fifo_intr(struct nouveau_subdev *);
+int  nv04_fifo_context_attach(struct nouveau_object *, struct nouveau_object *);
 
 #endif