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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2016-05-17 17:27:29 (GMT) |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2016-05-17 17:27:29 (GMT) |
| commit | ede40902cf80714ece199977b308e2ee437cae0b (patch) | |
| tree | e85e57194e7c9c7575ed0fa27b72495135a7eb23 /drivers/irqchip/irq-bcm2836.c | |
| parent | 91e8d0cbc94f81f110e508c3105dd93fb146d6b5 (diff) | |
| parent | 0097852c302aca943a8b76f7f85e133af6e1701a (diff) | |
| download | linux-ede40902cf80714ece199977b308e2ee437cae0b.tar.xz | |
Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner:
"This update delivers:
- Yet another interrupt chip diver (LPC32xx)
- Core functions to handle partitioned per-cpu interrupts
- Enhancements to the IPI core
- Proper handling of irq type configuration
- A large set of ARM GIC enhancements
- The usual pile of small fixes, cleanups and enhancements"
* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (31 commits)
irqchip/bcm2836: Use a more generic memory barrier call
irqchip/bcm2836: Fix compiler warning on 64-bit build
irqchip/bcm2836: Drop smp_set_ops on arm64 builds
irqchip/gic: Add helper functions for GIC setup and teardown
irqchip/gic: Store GIC configuration parameters
irqchip/gic: Pass GIC pointer to save/restore functions
irqchip/gic: Return an error if GIC initialisation fails
irqchip/gic: Remove static irq_chip definition for eoimode1
irqchip/gic: Don't initialise chip if mapping IO space fails
irqchip/gic: WARN if setting the interrupt type for a PPI fails
irqchip/gic: Don't unnecessarily write the IRQ configuration
irqchip: Mask the non-type/sense bits when translating an IRQ
genirq: Ensure IRQ descriptor is valid when setting-up the IRQ
irqchip/gic-v3: Configure all interrupts as non-secure Group-1
irqchip/gic-v2m: Add workaround for Broadcom NS2 GICv2m erratum
irqchip/irq-alpine-msi: Don't use <asm-generic/msi.h>
irqchip/mbigen: Checking for IS_ERR() instead of NULL
irqchip/gic-v3: Remove inexistant register definition
irqchip/gicv3-its: Don't allow devices whose ID is outside range
irqchip: Add LPC32xx interrupt controller driver
...
Diffstat (limited to 'drivers/irqchip/irq-bcm2836.c')
| -rw-r--r-- | drivers/irqchip/irq-bcm2836.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/drivers/irqchip/irq-bcm2836.c b/drivers/irqchip/irq-bcm2836.c index b6e950d..72ff1d5 100644 --- a/drivers/irqchip/irq-bcm2836.c +++ b/drivers/irqchip/irq-bcm2836.c @@ -195,7 +195,7 @@ static void bcm2836_arm_irqchip_send_ipi(const struct cpumask *mask, * Ensure that stores to normal memory are visible to the * other CPUs before issuing the IPI. */ - dsb(); + smp_wmb(); for_each_cpu(cpu, mask) { writel(1 << ipi, mailbox0_base + 16 * cpu); @@ -223,6 +223,7 @@ static struct notifier_block bcm2836_arm_irqchip_cpu_notifier = { .priority = 100, }; +#ifdef CONFIG_ARM int __init bcm2836_smp_boot_secondary(unsigned int cpu, struct task_struct *idle) { @@ -238,7 +239,7 @@ int __init bcm2836_smp_boot_secondary(unsigned int cpu, static const struct smp_operations bcm2836_smp_ops __initconst = { .smp_boot_secondary = bcm2836_smp_boot_secondary, }; - +#endif #endif static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = { @@ -252,12 +253,15 @@ bcm2836_arm_irqchip_smp_init(void) /* Unmask IPIs to the boot CPU. */ bcm2836_arm_irqchip_cpu_notify(&bcm2836_arm_irqchip_cpu_notifier, CPU_STARTING, - (void *)smp_processor_id()); + (void *)(uintptr_t)smp_processor_id()); register_cpu_notifier(&bcm2836_arm_irqchip_cpu_notifier); set_smp_cross_call(bcm2836_arm_irqchip_send_ipi); + +#ifdef CONFIG_ARM smp_set_ops(&bcm2836_smp_ops); #endif +#endif } /* |