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authorLinus Torvalds <torvalds@linux-foundation.org>2015-09-27 22:22:34 (GMT)
committerLinus Torvalds <torvalds@linux-foundation.org>2015-09-27 22:22:34 (GMT)
commit097f70b3c4d84ffccca15195bdfde3a37c0a7c0f (patch)
tree3338a83e351c980400bb524073b2bdfb5b0148be /drivers/irqchip
parente3be4266d3488cbbaddf7fcc661f4473db341e46 (diff)
parente060f6ed281669b6d2f22d8dafd664b532386918 (diff)
downloadlinux-097f70b3c4d84ffccca15195bdfde3a37c0a7c0f.tar.xz
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS fixes from Ralf Baechle: - Properly setup irq handling for ATH79 platforms - Fix bootmem mapstart calculation for contiguous maps - Handle little endian and older CPUs correct in BPF - Fix console for Fulong 2E systems - Handle FTLB correctly on R6 CPUs - Fixes for CM, GIC and MAAR support code * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: Initialise MAARs on secondary CPUs MIPS: print MAAR configuration during boot MIPS: mm: compile maar_init unconditionally irqchip: mips-gic: Fix pending & mask reads for MIPS64 with 32b GIC. irqchip: mips-gic: Convert CPU numbers to VP IDs. MIPS: CM: Provide a function to map from CPU to VP ID. MIPS: Fix FTLB detection for R6 MIPS: cpu-features: Add cpu_has_ftlb MIPS: ATH79: Add irq chip ar7240-misc-intc MIPS: ATH79: Set missing irq ack handler for ar7100-misc-intc irq chip MIPS: BPF: Fix build on pre-R2 little endian CPUs MIPS: BPF: Avoid unreachable code on little endian MIPS: bootmem: Fix mapstart calculation for contiguous maps MIPS: Fix console output for Fulong2e system
Diffstat (limited to 'drivers/irqchip')
-rw-r--r--drivers/irqchip/irq-mips-gic.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index af2f16b..aeaa061 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -320,6 +320,14 @@ static void gic_handle_shared_int(bool chained)
intrmask[i] = gic_read(intrmask_reg);
pending_reg += gic_reg_step;
intrmask_reg += gic_reg_step;
+
+ if (!config_enabled(CONFIG_64BIT) || mips_cm_is64)
+ continue;
+
+ pending[i] |= (u64)gic_read(pending_reg) << 32;
+ intrmask[i] |= (u64)gic_read(intrmask_reg) << 32;
+ pending_reg += gic_reg_step;
+ intrmask_reg += gic_reg_step;
}
bitmap_and(pending, pending, intrmask, gic_shared_intrs);
@@ -426,7 +434,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
spin_lock_irqsave(&gic_lock, flags);
/* Re-route this IRQ */
- gic_map_to_vpe(irq, cpumask_first(&tmp));
+ gic_map_to_vpe(irq, mips_cm_vp_id(cpumask_first(&tmp)));
/* Update the pcpu_masks */
for (i = 0; i < NR_CPUS; i++)
@@ -599,7 +607,7 @@ static __init void gic_ipi_init_one(unsigned int intr, int cpu,
GIC_SHARED_TO_HWIRQ(intr));
int i;
- gic_map_to_vpe(intr, cpu);
+ gic_map_to_vpe(intr, mips_cm_vp_id(cpu));
for (i = 0; i < NR_CPUS; i++)
clear_bit(intr, pcpu_masks[i].pcpu_mask);
set_bit(intr, pcpu_masks[cpu].pcpu_mask);