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| author | Bjorn Helgaas <bhelgaas@google.com> | 2013-08-27 15:54:40 (GMT) |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2013-08-28 17:28:22 (GMT) |
| commit | d3694d4fa3f44f6a295f8ab064937c8a1549d174 (patch) | |
| tree | 84ef7e23578a22d0819f5f2064bf813e071d43eb /drivers/memory | |
| parent | bd6fb762b595fb83758ae50d3610223244234a2d (diff) | |
| download | linux-d3694d4fa3f44f6a295f8ab064937c8a1549d174.tar.xz | |
PCI: Allow PCIe Capability link-related register access for switches
Every PCIe device has a link, except Root Complex Integrated Endpoints
and Root Complex Event Collectors. Previously we didn't give access
to PCIe capability link-related registers for Upstream Ports, Downstream
Ports, and Bridges, so attempts to read PCI_EXP_LNKCTL incorrectly
returned zero. See PCIe spec r3.0, sec 7.8 and 1.3.2.3.
Reference: http://lkml.kernel.org/r/979A8436335E3744ADCD3A9F2A2B68A52AD136BE@SJEXCHMB10.corp.ad.broadcom.com
Reported-by: Yuval Mintz <yuvalmin@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-By: Jiang Liu <jiang.liu@huawei.com>
Diffstat (limited to 'drivers/memory')
0 files changed, 0 insertions, 0 deletions