diff options
| author | Lucas Stach <dev@lynxeye.de> | 2015-12-22 18:41:01 (GMT) |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2015-12-28 13:14:56 (GMT) |
| commit | 74cd42bcad7486664d13b1b42bc81a399d7ed763 (patch) | |
| tree | d09a5a03f18bb0e41e5d2efc10d89e411d66242b /drivers/mmc | |
| parent | a8e326a911d3ca1b7480aca936956a4e89c4add5 (diff) | |
| download | linux-74cd42bcad7486664d13b1b42bc81a399d7ed763.tar.xz | |
mmc: tegra: disable SPI_MODE_CLKEN
The Tegra30 and up TRM states that this bit should always be
programmed to 0 by driver software.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/host/sdhci-tegra.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index f11db83..20ce81b 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -28,6 +28,10 @@ #include "sdhci-pltfm.h" /* Tegra SDHOST controller vendor register definitions */ +#define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 +#define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) +#define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) + #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 @@ -125,7 +129,7 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_tegra *tegra_host = pltfm_host->priv; const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; - u32 misc_ctrl; + u32 misc_ctrl, clk_ctrl; sdhci_reset(host, mask); @@ -145,6 +149,10 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104; sdhci_writew(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); + clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); + clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE; + sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); + tegra_host->ddr_signaling = false; } |