diff options
| author | Vincent Wan <vincent.wan@amd.com> | 2014-11-05 06:09:00 (GMT) |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2014-11-26 13:30:28 (GMT) |
| commit | 9b8ffea6efb0d0edcac265a1ca422188fc1b6dfb (patch) | |
| tree | a07d0b69bb64491bee30c2d90e8fa3c24c773797 /drivers/mmc | |
| parent | ad89fcb290b0b121a3de96d8c5d5f13a23663875 (diff) | |
| download | linux-9b8ffea6efb0d0edcac265a1ca422188fc1b6dfb.tar.xz | |
mmc: sdhci: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data
SDHC controller in AMD chipsets require SDHC transfer mode
register to be cleared for commands without data. The issue was
uncovered during testing eMMC cards on KB/ML based platforms
Signed-off-by: Vincent Wan <vincent.wan@amd.com>
Signed-off-by: Wan Zongshun <mcuos.com@gmail.com>
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Tested-by: Vikram B <vikram.b@amd.com>
Tested-by: Raghavendra Swamy <raghavendra.swamy@amd.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/host/sdhci.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index f895ab0..a743d52 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -915,10 +915,15 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host, struct mmc_data *data = cmd->data; if (data == NULL) { + if (host->quirks2 & + SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) { + sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); + } else { /* clear Auto CMD settings for no data CMDs */ - mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); - sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | + mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); + sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); + } return; } |