diff options
| author | Suresh Gupta <suresh.gupta@nxp.com> | 2017-04-28 12:32:09 (GMT) |
|---|---|---|
| committer | Xie Xiaobo <xiaobo.xie@nxp.com> | 2017-09-25 07:25:33 (GMT) |
| commit | 2fca68931a28cba56cd9053be296be85389d05d4 (patch) | |
| tree | 0d0384dc3a018ef6ed8128c201e0a50edf74df2d /drivers/mtd | |
| parent | 869d3874970612a09ceaed8747e2637daae60cea (diff) | |
| download | linux-2fca68931a28cba56cd9053be296be85389d05d4.tar.xz | |
mtd:spi_nor: Disable Micron flash HW protection
For Micron family ,The status register write enable/disable bit,
provides hardware data protection for the device
When the enable/disable bit is set to 1, the status register
nonvolatile bits become read-only and the WRITE STATUS REGISTER
operation will not execute.
Signed-off-by: Yunhui Cui <B56489@freescale.com>
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/spi-nor/spi-nor.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 20b8150..e32d6db 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -40,6 +40,8 @@ #define SPI_NOR_MAX_ID_LEN 6 #define SPI_NOR_MAX_ADDR_WIDTH 4 +#define SPI_NOR_MICRON_WRITE_ENABLE 0x7f + struct flash_info { char *name; @@ -1605,6 +1607,13 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) write_sr(nor, 0); spi_nor_wait_till_ready(nor); } + if (JEDEC_MFR(info) == SNOR_MFR_MICRON) { + ret = read_sr(nor); + ret &= SPI_NOR_MICRON_WRITE_ENABLE; + + write_enable(nor); + write_sr(nor, ret) + } if (!mtd->name) mtd->name = dev_name(dev); |