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authorYunhui Cui <yunhui.cui@nxp.com>2016-03-10 03:33:40 (GMT)
committerXie Xiaobo <xiaobo.xie@nxp.com>2017-09-25 07:25:31 (GMT)
commit68fed1e59c93d44bdbc5803616a5340d085ef858 (patch)
treee19fd772c2e4c326bb921dd659a60eb0cbd9e7c4 /drivers/mtd
parent383e0ab2de49b36bda8b14c8b99b4a9220382979 (diff)
downloadlinux-68fed1e59c93d44bdbc5803616a5340d085ef858.tar.xz
mtd: fsl-quadspi: add multi flash chip R/W on ls2080a
There is a hardware feature that qspi_amba_base is added internally by SOC design on ls2080a. so memmap_phy need not be added in driver. If memmap_phy is added, the flash A1 addr space is [0, memmap_phy] which far more than flash size. The AMBA memory will be divided into four parts and assign to every chipselect. Every channel will has two valid chipselects. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/spi-nor/fsl-quadspi.c14
1 files changed, 10 insertions, 4 deletions
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index b37b55d..f2379d18 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -703,11 +703,17 @@ static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
{
int nor_size = q->nor_size;
void __iomem *base = q->iobase;
+ u32 mem_base;
- qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
- qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
- qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
- qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
+ if (has_added_amba_base_internal(q))
+ mem_base = 0x0;
+ else
+ mem_base = q->memmap_phy;
+
+ qspi_writel(q, nor_size + mem_base, base + QUADSPI_SFA1AD);
+ qspi_writel(q, nor_size * 2 + mem_base, base + QUADSPI_SFA2AD);
+ qspi_writel(q, nor_size * 3 + mem_base, base + QUADSPI_SFB1AD);
+ qspi_writel(q, nor_size * 4 + mem_base, base + QUADSPI_SFB2AD);
}
/*