diff options
| author | Sujith Manoharan <c_manoha@qca.qualcomm.com> | 2013-12-06 10:58:40 (GMT) |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2013-12-09 20:37:56 (GMT) |
| commit | 4a878b9f8916eaeb5f8cea1379956b485e32450f (patch) | |
| tree | fd2a6f51dcfc7cabd312e046a92777f3500a2018 /drivers/net/wireless/ath/ath9k/ar9003_hw.c | |
| parent | 98b2e1fdf1603f30db195a11cc1ffcc2170d42a8 (diff) | |
| download | linux-4a878b9f8916eaeb5f8cea1379956b485e32450f.tar.xz | |
ath9k: Initialize baseband for DFS channels
Certain baseband registers require different values
to be programmed when operating in a DFS channel to
ensure that radar detection works correctly. This
is required for AR9300, AR9340 and AR9580.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9003_hw.c')
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_hw.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c index d8c1eee..4e8ae4a 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c @@ -152,6 +152,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) ar9340Modes_fast_clock_1p0); INIT_INI_ARRAY(&ah->iniCckfirJapan2484, ar9340_1p0_baseband_core_txfir_coeff_japan_2484); + INIT_INI_ARRAY(&ah->ini_dfs, + ar9340_1p0_baseband_postamble_dfs_channel); if (!ah->is_clk_25mhz) INIT_INI_ARRAY(&ah->iniAdditional, @@ -340,6 +342,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) ar9580_1p0_modes_fast_clock); INIT_INI_ARRAY(&ah->iniCckfirJapan2484, ar9580_1p0_baseband_core_txfir_coeff_japan_2484); + INIT_INI_ARRAY(&ah->ini_dfs, + ar9580_1p0_baseband_postamble_dfs_channel); } else if (AR_SREV_9565_11_OR_LATER(ah)) { INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9565_1p1_mac_core); @@ -458,6 +462,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) ar9300Modes_fast_clock_2p2); INIT_INI_ARRAY(&ah->iniCckfirJapan2484, ar9300_2p2_baseband_core_txfir_coeff_japan_2484); + INIT_INI_ARRAY(&ah->ini_dfs, + ar9300_2p2_baseband_postamble_dfs_channel); } } |