diff options
| author | Michael Chan <mchan@broadcom.com> | 2007-02-13 20:18:15 (GMT) |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2007-02-13 20:18:15 (GMT) |
| commit | 569a5df8597deeaa39867be73c7305fd82522f57 (patch) | |
| tree | a49d58a45867f7255faf3c08d00830618b4d73c3 /drivers/net | |
| parent | 5129724aa5de3a71fc70e71ca49d542ca1a5aa1e (diff) | |
| download | linux-569a5df8597deeaa39867be73c7305fd82522f57.tar.xz | |
[TG3]: Use constant for PHY register 0x1e.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/tg3.c | 10 | ||||
| -rw-r--r-- | drivers/net/tg3.h | 1 |
2 files changed, 7 insertions, 4 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 604f308..a1aeba2 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -6594,8 +6594,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) u32 tmp; /* Clear CRC stats. */ - if (!tg3_readphy(tp, 0x1e, &tmp)) { - tg3_writephy(tp, 0x1e, tmp | 0x8000); + if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { + tg3_writephy(tp, MII_TG3_TEST1, + tmp | MII_TG3_TEST1_CRC_EN); tg3_readphy(tp, 0x14, &tmp); } } @@ -7419,8 +7420,9 @@ static unsigned long calc_crc_errors(struct tg3 *tp) u32 val; spin_lock_bh(&tp->lock); - if (!tg3_readphy(tp, 0x1e, &val)) { - tg3_writephy(tp, 0x1e, val | 0x8000); + if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { + tg3_writephy(tp, MII_TG3_TEST1, + val | MII_TG3_TEST1_CRC_EN); tg3_readphy(tp, 0x14, &val); } else val = 0; diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index 80f59ac..45d477e 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h @@ -1660,6 +1660,7 @@ #define MII_TG3_TEST1 0x1e #define MII_TG3_TEST1_TRIM_EN 0x0010 +#define MII_TG3_TEST1_CRC_EN 0x8000 /* There are two ways to manage the TX descriptors on the tigon3. * Either the descriptors are in host DMA'able memory, or they |