diff options
| author | Zhou Wang <wangzhou1@hisilicon.com> | 2015-10-30 00:56:58 (GMT) |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2015-11-02 20:49:18 (GMT) |
| commit | 9cdce1cdc0c40e6c2e85ed9ca13c32adaa5fe0c5 (patch) | |
| tree | bdb0489a8034f7449e3a9f2b4c740cca15bfb5ae /drivers/pci/host/pcie-designware.h | |
| parent | 883cc17cb193ad73bbc57934aa8d750162a9b79a (diff) | |
| download | linux-9cdce1cdc0c40e6c2e85ed9ca13c32adaa5fe0c5.tar.xz | |
Revert "PCI: designware: Program ATU with untranslated address"
Revert f4c55c5a3f7f ("PCI: designware: Program ATU with untranslated
address").
Note that dra7xx_pcie_host_init() now modifies pp->io_base, but we still
need the original value for dw_pcie_setup() in the path below, so this adds
a new io_base_tmp member. It will be removed later when dw_pcie_setup() is
removed.
dra7xx_add_pcie_port
dw_pcie_host_init
pp->io_base = range.cpu_addr
pp->io_base_tmp = range.cpu_addr # <-- added
pp->ops->host_init
dra7xx_pcie_host_init # ops->host_init
pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR # <-- modified
pci_common_init_dev(..., &dw_pci)
pcibios_init_hw
hw->setup
dw_pcie_setup # hw_pci.setup
pci_ioremap_io(..., pp->io_base_tmp) # <-- original addr required
[bhelgaas: changelog]
Tested-by: James Morse <james.morse@arm.com>
Tested-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Tested-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
Diffstat (limited to 'drivers/pci/host/pcie-designware.h')
| -rw-r--r-- | drivers/pci/host/pcie-designware.h | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index e7b3279..f21dc28 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -27,19 +27,16 @@ struct pcie_port { u8 root_bus_nr; void __iomem *dbi_base; u64 cfg0_base; - u64 cfg0_mod_base; void __iomem *va_cfg0_base; u32 cfg0_size; u64 cfg1_base; - u64 cfg1_mod_base; void __iomem *va_cfg1_base; u32 cfg1_size; u64 io_base; - u64 io_mod_base; + u64 io_base_tmp; phys_addr_t io_bus_addr; u32 io_size; u64 mem_base; - u64 mem_mod_base; phys_addr_t mem_bus_addr; u32 mem_size; struct resource cfg; |