diff options
| author | Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> | 2010-04-15 04:17:33 (GMT) |
|---|---|---|
| committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2010-05-11 19:01:34 (GMT) |
| commit | f647a44f5725b0e6c8211096f4b49900164123ee (patch) | |
| tree | dc5e677d978435159dd62e1faf0824fb01e44aa0 /drivers/pci/pcie/aer | |
| parent | 17e21854bd59862f4ee47d1c7e828549f782711b (diff) | |
| download | linux-f647a44f5725b0e6c8211096f4b49900164123ee.tar.xz | |
PCI: aerdrv: redefine PCI_ERR_ROOT_*_SRC
The Error Source Identification Register (Offset 34h) is 4 byte
which contains a couple of 2 byte field, "[15:0] ERR_COR Source
Identification" and "[31:16] ERR_FATAL/NONFATAL Source Identification."
This patch defines PCI_ERR_ROOT_ERR_SRC to make dword access sensible.
Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/pci/pcie/aer')
| -rw-r--r-- | drivers/pci/pcie/aer/aer_inject.c | 2 | ||||
| -rw-r--r-- | drivers/pci/pcie/aer/aerdrv.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pci/pcie/aer/aer_inject.c b/drivers/pci/pcie/aer/aer_inject.c index f8f425b..9099246 100644 --- a/drivers/pci/pcie/aer/aer_inject.c +++ b/drivers/pci/pcie/aer/aer_inject.c @@ -168,7 +168,7 @@ static u32 *find_pci_config_dword(struct aer_error *err, int where, target = &err->root_status; rw1cs = 1; break; - case PCI_ERR_ROOT_COR_SRC: + case PCI_ERR_ROOT_ERR_SRC: target = &err->source_id; break; } diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c index b69dbdc..1a55c16 100644 --- a/drivers/pci/pcie/aer/aerdrv.c +++ b/drivers/pci/pcie/aer/aerdrv.c @@ -210,7 +210,7 @@ irqreturn_t aer_irq(int irq, void *context) } /* Read error source and clear error status */ - pci_read_config_dword(pdev->port, pos + PCI_ERR_ROOT_COR_SRC, &id); + pci_read_config_dword(pdev->port, pos + PCI_ERR_ROOT_ERR_SRC, &id); pci_write_config_dword(pdev->port, pos + PCI_ERR_ROOT_STATUS, status); /* Store error source for later DPC handler */ |