diff options
author | Jon Mason <jon.mason@broadcom.com> | 2017-04-04 19:32:33 (GMT) |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2017-04-12 10:41:21 (GMT) |
commit | 28dd2313a6e4144a3cd41bc112b2d951dcf09a53 (patch) | |
tree | ec79b8b9cb74597c3e30229c25b897b861b77503 /drivers/pci/quirks.c | |
parent | 35b366d584da2a82444f73d8c17d5afb84b3f8e2 (diff) | |
download | linux-28dd2313a6e4144a3cd41bc112b2d951dcf09a53.tar.xz |
PCI: Add Broadcom Northstar2 PAXC quirk for device class and MPSS
[ Upstream commit ce709f86501a013e941e9986cb072eae375ddf3e ]
The Broadcom Northstar2 SoC has a number of quirks for the PAXC
(internal/fake) PCI bus. Specifically, the PCI config space is shared
between the root port and the first PF (ie., PF0), and a number of fields
are tied to zero (thus preventing them from being set). These cannot be
"fixed" in device firmware, so we must fix them with a quirk.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/pci/quirks.c')
-rw-r--r-- | drivers/pci/quirks.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 19a35fa..71905ed 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2240,6 +2240,27 @@ DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5719, quirk_brcm_5719_limit_mrrs); +#ifdef CONFIG_PCIE_IPROC_PLATFORM +static void quirk_paxc_bridge(struct pci_dev *pdev) +{ + /* The PCI config space is shared with the PAXC root port and the first + * Ethernet device. So, we need to workaround this by telling the PCI + * code that the bridge is not an Ethernet device. + */ + if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) + pdev->class = PCI_CLASS_BRIDGE_PCI << 8; + + /* MPSS is not being set properly (as it is currently 0). This is + * because that area of the PCI config space is hard coded to zero, and + * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS) + * so that the MPS can be set to the real max value. + */ + pdev->pcie_mpss = 2; +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge); +#endif + /* Originally in EDAC sources for i82875P: * Intel tells BIOS developers to hide device 6 which * configures the overflow device access containing |