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authorPo Liu <po.liu@nxp.com>2017-05-22 07:46:02 (GMT)
committerXie Xiaobo <xiaobo.xie@nxp.com>2017-09-25 07:25:29 (GMT)
commit5be0fc5c16f3588d138aee7165f54abdb2fba01d (patch)
tree87c5c806051f65d9a49ee73ad5bce751c97a24be /drivers/pci
parent9c2aa654e19e2ac73bb89dc365e48e5b3e906f3f (diff)
downloadlinux-5be0fc5c16f3588d138aee7165f54abdb2fba01d.tar.xz
pci:add support aer/pme interrupts with none MSI/MSI-X/INTx mode
[pcie part] On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode. When chip support the aer/pme interrupts with none MSI/MSI-X/INTx mode, maybe there is interrupt line for aer pme etc. Search the interrupt number in the fdt file. Then fixup the dev->irq with it. Signed-off-by: Po Liu <po.liu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/pcie/portdrv_core.c29
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index cea504f..1bad877 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -44,6 +44,20 @@ static void release_pcie_device(struct device *dev)
}
/**
+ * pcibios_check_service_irqs - check irqs in the device tree
+ * @dev: PCI Express port to handle
+ * @irqs: Array of irqs to populate
+ * @mask: Bitmask of port capabilities returned by get_port_device_capability()
+ *
+ * Return value: 0 means no service irqs in the device tree
+ *
+ */
+int __weak pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
+{
+ return 0;
+}
+
+/**
* pcie_port_enable_msix - try to set up MSI-X as interrupt mode for given port
* @dev: PCI Express port to handle
* @irqs: Array of interrupt vectors to populate
@@ -148,10 +162,25 @@ static int pcie_init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
{
unsigned flags = PCI_IRQ_LEGACY | PCI_IRQ_MSI;
int ret, i;
+ int irq = -1;
for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
irqs[i] = -1;
+ /* Check if some platforms owns independent irq pins for AER/PME etc.
+ * Some platforms may own independent AER/PME interrupts and set
+ * them in the device tree file.
+ */
+ ret = pcibios_check_service_irqs(dev, irqs, mask);
+ if (ret) {
+ if (dev->irq)
+ irq = dev->irq;
+ for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
+ if (irqs[i] == -1 && i != PCIE_PORT_SERVICE_VC_SHIFT)
+ irqs[i] = irq;
+ return 0;
+ }
+
/*
* If MSI cannot be used for PCIe PME or hotplug, we have to use
* INTx or other interrupts, e.g. system shared interrupt.