diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-04-01 20:10:49 (GMT) |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-04-01 20:10:49 (GMT) |
commit | d64b3932531cbc0c9d6bdb744446934435e9d6af (patch) | |
tree | 32220446dde284e82f26616b852fa51fd8d0111d /drivers/pinctrl/sh-pfc | |
parent | 4dedde7c7a18f55180574f934dbc1be84ca0400b (diff) | |
parent | 43f23a0660fa0fdc74c7b1bfc5a209883dbf8153 (diff) | |
download | linux-d64b3932531cbc0c9d6bdb744446934435e9d6af.tar.xz |
Merge tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control bulk changes from Linus Walleij:
"Pin control bulk changes for the v3.15 series, no new core
functionality this time, just incremental driver updates:
- A large refactoring of the MVEBU (Marvell) driver.
- A large refactoring of the Tegra (nVidia) driver.
- GPIO interrupt including soft edges support in the STi driver.
- Misc updates to PFC (Renesas), AT91, ADI2 (Blackfin),
pinctrl-single, sirf (CSR), msm (Qualcomm), Exynos (Samsung), sunxi
(AllWinner), i.MX (Freescale), Baytrail"
* tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits)
pinctrl: tegra: add some missing Tegra114 entries
pinctrl: tegra: fix some mistakes in Tegra124
pinctrl: msm: fix up out-of-order merge conflict
pinctrl: st: Fix error check for of_irq_to_resource usage
pinctrl: tegra: consistency cleanup
pinctrl: tegra: dynamically calculate function list of groups
pinctrl: tegra: init Tegra20/30 at module_init time
pinctrl: st: Use ARRAY_SIZE instead of raw value for number of delays
pinctrl: st: add pinctrl support for the STiH407 SoC
pinctrl: st: Enhance the controller to manage unavailable registers
pinctrl: msm: Simplify msm_config_reg() and callers
pinctrl: msm: Remove impossible WARN_ON()s
pinctrl: msm: Replace lookup tables with math
pinctrl: msm: Drop OF_IRQ dependency
pinctrl: msm: Drop unused includes
pinctrl: msm: Check for ngpios > MAX_NR_GPIO
pinctrl: msm: Silence recursive lockdep warning
pinctrl: mvebu: silence WARN to dev_warn
pinctrl: msm: drop wake_irqs bitmap
pinctrl-baytrail: add function mux checking in gpio pin request
...
Diffstat (limited to 'drivers/pinctrl/sh-pfc')
-rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 171 | ||||
-rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 596 |
2 files changed, 767 insertions, 0 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index c381ae6..4809371 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -2260,6 +2260,42 @@ static const unsigned int msiof0_tx_pins[] = { static const unsigned int msiof0_tx_mux[] = { MSIOF0_TXD_MARK, }; + +static const unsigned int msiof0_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 23), +}; +static const unsigned int msiof0_clk_b_mux[] = { + MSIOF0_SCK_B_MARK, +}; +static const unsigned int msiof0_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(1, 12), +}; +static const unsigned int msiof0_ss1_b_mux[] = { + MSIOF0_SS1_B_MARK, +}; +static const unsigned int msiof0_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(1, 10), +}; +static const unsigned int msiof0_ss2_b_mux[] = { + MSIOF0_SS2_B_MARK, +}; +static const unsigned int msiof0_rx_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(1, 29), +}; +static const unsigned int msiof0_rx_b_mux[] = { + MSIOF0_RXD_B_MARK, +}; +static const unsigned int msiof0_tx_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(1, 28), +}; +static const unsigned int msiof0_tx_b_mux[] = { + MSIOF0_TXD_B_MARK, +}; /* - MSIOF1 ----------------------------------------------------------------- */ static const unsigned int msiof1_clk_pins[] = { /* SCK */ @@ -2303,6 +2339,42 @@ static const unsigned int msiof1_tx_pins[] = { static const unsigned int msiof1_tx_mux[] = { MSIOF1_TXD_MARK, }; + +static const unsigned int msiof1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 16), +}; +static const unsigned int msiof1_clk_b_mux[] = { + MSIOF1_SCK_B_MARK, +}; +static const unsigned int msiof1_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(0, 18), +}; +static const unsigned int msiof1_ss1_b_mux[] = { + MSIOF1_SS1_B_MARK, +}; +static const unsigned int msiof1_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(0, 19), +}; +static const unsigned int msiof1_ss2_b_mux[] = { + MSIOF1_SS2_B_MARK, +}; +static const unsigned int msiof1_rx_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(1, 17), +}; +static const unsigned int msiof1_rx_b_mux[] = { + MSIOF1_RXD_B_MARK, +}; +static const unsigned int msiof1_tx_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 20), +}; +static const unsigned int msiof1_tx_b_mux[] = { + MSIOF1_TXD_B_MARK, +}; /* - MSIOF2 ----------------------------------------------------------------- */ static const unsigned int msiof2_clk_pins[] = { /* SCK */ @@ -2389,6 +2461,58 @@ static const unsigned int msiof3_tx_pins[] = { static const unsigned int msiof3_tx_mux[] = { MSIOF3_TXD_MARK, }; + +static const unsigned int msiof3_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 0), +}; +static const unsigned int msiof3_clk_b_mux[] = { + MSIOF3_SCK_B_MARK, +}; +static const unsigned int msiof3_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(0, 1), +}; +static const unsigned int msiof3_sync_b_mux[] = { + MSIOF3_SYNC_B_MARK, +}; +static const unsigned int msiof3_rx_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 2), +}; +static const unsigned int msiof3_rx_b_mux[] = { + MSIOF3_RXD_B_MARK, +}; +static const unsigned int msiof3_tx_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 3), +}; +static const unsigned int msiof3_tx_b_mux[] = { + MSIOF3_TXD_B_MARK, +}; +/* - QSPI ------------------------------------------------------------------- */ +static const unsigned int qspi_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), +}; +static const unsigned int qspi_ctrl_mux[] = { + SPCLK_MARK, SSL_MARK, +}; +static const unsigned int qspi_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), +}; +static const unsigned int qspi_data2_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, +}; +static const unsigned int qspi_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 8), +}; +static const unsigned int qspi_data4_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, +}; /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX, TX */ @@ -3231,6 +3355,13 @@ static const unsigned int usb0_pins[] = { static const unsigned int usb0_mux[] = { USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, }; +static const unsigned int usb0_ovc_vbus_pins[] = { + /* OVC/VBUS */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int usb0_ovc_vbus_mux[] = { + USB0_OVC_VBUS_MARK, +}; /* - USB1 ------------------------------------------------------------------- */ static const unsigned int usb1_pins[] = { /* PWEN, OVC */ @@ -3653,12 +3784,22 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof0_ss2), SH_PFC_PIN_GROUP(msiof0_rx), SH_PFC_PIN_GROUP(msiof0_tx), + SH_PFC_PIN_GROUP(msiof0_clk_b), + SH_PFC_PIN_GROUP(msiof0_ss1_b), + SH_PFC_PIN_GROUP(msiof0_ss2_b), + SH_PFC_PIN_GROUP(msiof0_rx_b), + SH_PFC_PIN_GROUP(msiof0_tx_b), SH_PFC_PIN_GROUP(msiof1_clk), SH_PFC_PIN_GROUP(msiof1_sync), SH_PFC_PIN_GROUP(msiof1_ss1), SH_PFC_PIN_GROUP(msiof1_ss2), SH_PFC_PIN_GROUP(msiof1_rx), SH_PFC_PIN_GROUP(msiof1_tx), + SH_PFC_PIN_GROUP(msiof1_clk_b), + SH_PFC_PIN_GROUP(msiof1_ss1_b), + SH_PFC_PIN_GROUP(msiof1_ss2_b), + SH_PFC_PIN_GROUP(msiof1_rx_b), + SH_PFC_PIN_GROUP(msiof1_tx_b), SH_PFC_PIN_GROUP(msiof2_clk), SH_PFC_PIN_GROUP(msiof2_sync), SH_PFC_PIN_GROUP(msiof2_ss1), @@ -3671,6 +3812,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof3_ss2), SH_PFC_PIN_GROUP(msiof3_rx), SH_PFC_PIN_GROUP(msiof3_tx), + SH_PFC_PIN_GROUP(msiof3_clk_b), + SH_PFC_PIN_GROUP(msiof3_sync_b), + SH_PFC_PIN_GROUP(msiof3_rx_b), + SH_PFC_PIN_GROUP(msiof3_tx_b), + SH_PFC_PIN_GROUP(qspi_ctrl), + SH_PFC_PIN_GROUP(qspi_data2), + SH_PFC_PIN_GROUP(qspi_data4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -3789,6 +3937,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tpu0_to2), SH_PFC_PIN_GROUP(tpu0_to3), SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb0_ovc_vbus), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb2), VIN_DATA_PIN_GROUP(vin0_data, 24), @@ -3941,6 +4090,11 @@ static const char * const msiof0_groups[] = { "msiof0_ss2", "msiof0_rx", "msiof0_tx", + "msiof0_clk_b", + "msiof0_ss1_b", + "msiof0_ss2_b", + "msiof0_rx_b", + "msiof0_tx_b", }; static const char * const msiof1_groups[] = { @@ -3950,6 +4104,11 @@ static const char * const msiof1_groups[] = { "msiof1_ss2", "msiof1_rx", "msiof1_tx", + "msiof1_clk_b", + "msiof1_ss1_b", + "msiof1_ss2_b", + "msiof1_rx_b", + "msiof1_tx_b", }; static const char * const msiof2_groups[] = { @@ -3968,6 +4127,16 @@ static const char * const msiof3_groups[] = { "msiof3_ss2", "msiof3_rx", "msiof3_tx", + "msiof3_clk_b", + "msiof3_sync_b", + "msiof3_rx_b", + "msiof3_tx_b", +}; + +static const char * const qspi_groups[] = { + "qspi_ctrl", + "qspi_data2", + "qspi_data4", }; static const char * const scif0_groups[] = { @@ -4134,6 +4303,7 @@ static const char * const tpu0_groups[] = { static const char * const usb0_groups[] = { "usb0", + "usb0_ovc_vbus", }; static const char * const usb1_groups[] = { @@ -4213,6 +4383,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 567d691..5186d70 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -1945,6 +1945,50 @@ static const unsigned int i2c4_c_pins[] = { static const unsigned int i2c4_c_mux[] = { SCL4_C_MARK, SDA4_C_MARK, }; +/* - I2C7 ------------------------------------------------------------------- */ +static const unsigned int i2c7_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), +}; +static const unsigned int i2c7_mux[] = { + SCL7_MARK, SDA7_MARK, +}; +static const unsigned int i2c7_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), +}; +static const unsigned int i2c7_b_mux[] = { + SCL7_B_MARK, SDA7_B_MARK, +}; +static const unsigned int i2c7_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), +}; +static const unsigned int i2c7_c_mux[] = { + SCL7_C_MARK, SDA7_C_MARK, +}; +/* - I2C8 ------------------------------------------------------------------- */ +static const unsigned int i2c8_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), +}; +static const unsigned int i2c8_mux[] = { + SCL8_MARK, SDA8_MARK, +}; +static const unsigned int i2c8_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), +}; +static const unsigned int i2c8_b_mux[] = { + SCL8_B_MARK, SDA8_B_MARK, +}; +static const unsigned int i2c8_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), +}; +static const unsigned int i2c8_c_mux[] = { + SCL8_C_MARK, SDA8_C_MARK, +}; /* - INTC ------------------------------------------------------------------- */ static const unsigned int intc_irq0_pins[] = { /* IRQ */ @@ -2051,6 +2095,92 @@ static const unsigned int msiof0_tx_pins[] = { static const unsigned int msiof0_tx_mux[] = { MSIOF0_TXD_MARK, }; + +static const unsigned int msiof0_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 16), +}; +static const unsigned int msiof0_clk_b_mux[] = { + MSIOF0_SCK_B_MARK, +}; +static const unsigned int msiof0_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(0, 17), +}; +static const unsigned int msiof0_sync_b_mux[] = { + MSIOF0_SYNC_B_MARK, +}; +static const unsigned int msiof0_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(0, 18), +}; +static const unsigned int msiof0_ss1_b_mux[] = { + MSIOF0_SS1_B_MARK, +}; +static const unsigned int msiof0_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(0, 19), +}; +static const unsigned int msiof0_ss2_b_mux[] = { + MSIOF0_SS2_B_MARK, +}; +static const unsigned int msiof0_rx_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 21), +}; +static const unsigned int msiof0_rx_b_mux[] = { + MSIOF0_RXD_B_MARK, +}; +static const unsigned int msiof0_tx_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 20), +}; +static const unsigned int msiof0_tx_b_mux[] = { + MSIOF0_TXD_B_MARK, +}; + +static const unsigned int msiof0_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 26), +}; +static const unsigned int msiof0_clk_c_mux[] = { + MSIOF0_SCK_C_MARK, +}; +static const unsigned int msiof0_sync_c_pins[] = { + /* SYNC */ + RCAR_GP_PIN(5, 25), +}; +static const unsigned int msiof0_sync_c_mux[] = { + MSIOF0_SYNC_C_MARK, +}; +static const unsigned int msiof0_ss1_c_pins[] = { + /* SS1 */ + RCAR_GP_PIN(5, 27), +}; +static const unsigned int msiof0_ss1_c_mux[] = { + MSIOF0_SS1_C_MARK, +}; +static const unsigned int msiof0_ss2_c_pins[] = { + /* SS2 */ + RCAR_GP_PIN(5, 28), +}; +static const unsigned int msiof0_ss2_c_mux[] = { + MSIOF0_SS2_C_MARK, +}; +static const unsigned int msiof0_rx_c_pins[] = { + /* RXD */ + RCAR_GP_PIN(5, 29), +}; +static const unsigned int msiof0_rx_c_mux[] = { + MSIOF0_RXD_C_MARK, +}; +static const unsigned int msiof0_tx_c_pins[] = { + /* TXD */ + RCAR_GP_PIN(5, 30), +}; +static const unsigned int msiof0_tx_c_mux[] = { + MSIOF0_TXD_C_MARK, +}; /* - MSIOF1 ----------------------------------------------------------------- */ static const unsigned int msiof1_clk_pins[] = { /* SCK */ @@ -2094,6 +2224,143 @@ static const unsigned int msiof1_tx_pins[] = { static const unsigned int msiof1_tx_mux[] = { MSIOF1_TXD_MARK, }; + +static const unsigned int msiof1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 29), +}; +static const unsigned int msiof1_clk_b_mux[] = { + MSIOF1_SCK_B_MARK, +}; +static const unsigned int msiof1_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(2, 30), +}; +static const unsigned int msiof1_sync_b_mux[] = { + MSIOF1_SYNC_B_MARK, +}; +static const unsigned int msiof1_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(2, 31), +}; +static const unsigned int msiof1_ss1_b_mux[] = { + MSIOF1_SS1_B_MARK, +}; +static const unsigned int msiof1_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(7, 16), +}; +static const unsigned int msiof1_ss2_b_mux[] = { + MSIOF1_SS2_B_MARK, +}; +static const unsigned int msiof1_rx_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(7, 18), +}; +static const unsigned int msiof1_rx_b_mux[] = { + MSIOF1_RXD_B_MARK, +}; +static const unsigned int msiof1_tx_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(7, 17), +}; +static const unsigned int msiof1_tx_b_mux[] = { + MSIOF1_TXD_B_MARK, +}; + +static const unsigned int msiof1_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 15), +}; +static const unsigned int msiof1_clk_c_mux[] = { + MSIOF1_SCK_C_MARK, +}; +static const unsigned int msiof1_sync_c_pins[] = { + /* SYNC */ + RCAR_GP_PIN(2, 16), +}; +static const unsigned int msiof1_sync_c_mux[] = { + MSIOF1_SYNC_C_MARK, +}; +static const unsigned int msiof1_rx_c_pins[] = { + /* RXD */ + RCAR_GP_PIN(2, 18), +}; +static const unsigned int msiof1_rx_c_mux[] = { + MSIOF1_RXD_C_MARK, +}; +static const unsigned int msiof1_tx_c_pins[] = { + /* TXD */ + RCAR_GP_PIN(2, 17), +}; +static const unsigned int msiof1_tx_c_mux[] = { + MSIOF1_TXD_C_MARK, +}; + +static const unsigned int msiof1_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 28), +}; +static const unsigned int msiof1_clk_d_mux[] = { + MSIOF1_SCK_D_MARK, +}; +static const unsigned int msiof1_sync_d_pins[] = { + /* SYNC */ + RCAR_GP_PIN(0, 30), +}; +static const unsigned int msiof1_sync_d_mux[] = { + MSIOF1_SYNC_D_MARK, +}; +static const unsigned int msiof1_ss1_d_pins[] = { + /* SS1 */ + RCAR_GP_PIN(0, 29), +}; +static const unsigned int msiof1_ss1_d_mux[] = { + MSIOF1_SS1_D_MARK, +}; +static const unsigned int msiof1_rx_d_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 27), +}; +static const unsigned int msiof1_rx_d_mux[] = { + MSIOF1_RXD_D_MARK, +}; +static const unsigned int msiof1_tx_d_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 26), +}; +static const unsigned int msiof1_tx_d_mux[] = { + MSIOF1_TXD_D_MARK, +}; + +static const unsigned int msiof1_clk_e_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 18), +}; +static const unsigned int msiof1_clk_e_mux[] = { + MSIOF1_SCK_E_MARK, +}; +static const unsigned int msiof1_sync_e_pins[] = { + /* SYNC */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int msiof1_sync_e_mux[] = { + MSIOF1_SYNC_E_MARK, +}; +static const unsigned int msiof1_rx_e_pins[] = { + /* RXD */ + RCAR_GP_PIN(5, 17), +}; +static const unsigned int msiof1_rx_e_mux[] = { + MSIOF1_RXD_E_MARK, +}; +static const unsigned int msiof1_tx_e_pins[] = { + /* TXD */ + RCAR_GP_PIN(5, 20), +}; +static const unsigned int msiof1_tx_e_mux[] = { + MSIOF1_TXD_E_MARK, +}; /* - MSIOF2 ----------------------------------------------------------------- */ static const unsigned int msiof2_clk_pins[] = { /* SCK */ @@ -2137,6 +2404,197 @@ static const unsigned int msiof2_tx_pins[] = { static const unsigned int msiof2_tx_mux[] = { MSIOF2_TXD_MARK, }; + +static const unsigned int msiof2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 0), +}; +static const unsigned int msiof2_clk_b_mux[] = { + MSIOF2_SCK_B_MARK, +}; +static const unsigned int msiof2_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(3, 1), +}; +static const unsigned int msiof2_sync_b_mux[] = { + MSIOF2_SYNC_B_MARK, +}; +static const unsigned int msiof2_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(3, 8), +}; +static const unsigned int msiof2_ss1_b_mux[] = { + MSIOF2_SS1_B_MARK, +}; +static const unsigned int msiof2_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(3, 9), +}; +static const unsigned int msiof2_ss2_b_mux[] = { + MSIOF2_SS2_B_MARK, +}; +static const unsigned int msiof2_rx_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(3, 17), +}; +static const unsigned int msiof2_rx_b_mux[] = { + MSIOF2_RXD_B_MARK, +}; +static const unsigned int msiof2_tx_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(3, 16), +}; +static const unsigned int msiof2_tx_b_mux[] = { + MSIOF2_TXD_B_MARK, +}; + +static const unsigned int msiof2_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 2), +}; +static const unsigned int msiof2_clk_c_mux[] = { + MSIOF2_SCK_C_MARK, +}; +static const unsigned int msiof2_sync_c_pins[] = { + /* SYNC */ + RCAR_GP_PIN(2, 3), +}; +static const unsigned int msiof2_sync_c_mux[] = { + MSIOF2_SYNC_C_MARK, +}; +static const unsigned int msiof2_rx_c_pins[] = { + /* RXD */ + RCAR_GP_PIN(2, 5), +}; +static const unsigned int msiof2_rx_c_mux[] = { + MSIOF2_RXD_C_MARK, +}; +static const unsigned int msiof2_tx_c_pins[] = { + /* TXD */ + RCAR_GP_PIN(2, 4), +}; +static const unsigned int msiof2_tx_c_mux[] = { + MSIOF2_TXD_C_MARK, +}; + +static const unsigned int msiof2_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 14), +}; +static const unsigned int msiof2_clk_d_mux[] = { + MSIOF2_SCK_D_MARK, +}; +static const unsigned int msiof2_sync_d_pins[] = { + /* SYNC */ + RCAR_GP_PIN(2, 15), +}; +static const unsigned int msiof2_sync_d_mux[] = { + MSIOF2_SYNC_D_MARK, +}; +static const unsigned int msiof2_ss1_d_pins[] = { + /* SS1 */ + RCAR_GP_PIN(2, 17), +}; +static const unsigned int msiof2_ss1_d_mux[] = { + MSIOF2_SS1_D_MARK, +}; +static const unsigned int msiof2_ss2_d_pins[] = { + /* SS2 */ + RCAR_GP_PIN(2, 19), +}; +static const unsigned int msiof2_ss2_d_mux[] = { + MSIOF2_SS2_D_MARK, +}; +static const unsigned int msiof2_rx_d_pins[] = { + /* RXD */ + RCAR_GP_PIN(2, 18), +}; +static const unsigned int msiof2_rx_d_mux[] = { + MSIOF2_RXD_D_MARK, +}; +static const unsigned int msiof2_tx_d_pins[] = { + /* TXD */ + RCAR_GP_PIN(2, 16), +}; +static const unsigned int msiof2_tx_d_mux[] = { + MSIOF2_TXD_D_MARK, +}; + +static const unsigned int msiof2_clk_e_pins[] = { + /* SCK */ + RCAR_GP_PIN(7, 15), +}; +static const unsigned int msiof2_clk_e_mux[] = { + MSIOF2_SCK_E_MARK, +}; +static const unsigned int msiof2_sync_e_pins[] = { + /* SYNC */ + RCAR_GP_PIN(7, 16), +}; +static const unsigned int msiof2_sync_e_mux[] = { + MSIOF2_SYNC_E_MARK, +}; +static const unsigned int msiof2_rx_e_pins[] = { + /* RXD */ + RCAR_GP_PIN(7, 14), +}; +static const unsigned int msiof2_rx_e_mux[] = { + MSIOF2_RXD_E_MARK, +}; +static const unsigned int msiof2_tx_e_pins[] = { + /* TXD */ + RCAR_GP_PIN(7, 13), +}; +static const unsigned int msiof2_tx_e_mux[] = { + MSIOF2_TXD_E_MARK, +}; +/* - QSPI ------------------------------------------------------------------- */ +static const unsigned int qspi_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), +}; +static const unsigned int qspi_ctrl_mux[] = { + SPCLK_MARK, SSL_MARK, +}; +static const unsigned int qspi_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), +}; +static const unsigned int qspi_data2_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, +}; +static const unsigned int qspi_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 8), +}; +static const unsigned int qspi_data4_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, +}; + +static const unsigned int qspi_ctrl_b_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5), +}; +static const unsigned int qspi_ctrl_b_mux[] = { + SPCLK_B_MARK, SSL_B_MARK, +}; +static const unsigned int qspi_data2_b_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), +}; +static const unsigned int qspi_data2_b_mux[] = { + MOSI_IO0_B_MARK, MISO_IO1_B_MARK, +}; +static const unsigned int qspi_data4_b_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), + RCAR_GP_PIN(6, 4), +}; +static const unsigned int qspi_data4_b_mux[] = { + SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK, + IO2_B_MARK, IO3_B_MARK, SSL_B_MARK, +}; /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX, TX */ @@ -3125,6 +3583,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c4), SH_PFC_PIN_GROUP(i2c4_b), SH_PFC_PIN_GROUP(i2c4_c), + SH_PFC_PIN_GROUP(i2c7), + SH_PFC_PIN_GROUP(i2c7_b), + SH_PFC_PIN_GROUP(i2c7_c), + SH_PFC_PIN_GROUP(i2c8), + SH_PFC_PIN_GROUP(i2c8_b), + SH_PFC_PIN_GROUP(i2c8_c), SH_PFC_PIN_GROUP(intc_irq0), SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), @@ -3139,18 +3603,75 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof0_ss2), SH_PFC_PIN_GROUP(msiof0_rx), SH_PFC_PIN_GROUP(msiof0_tx), + SH_PFC_PIN_GROUP(msiof0_clk_b), + SH_PFC_PIN_GROUP(msiof0_sync_b), + SH_PFC_PIN_GROUP(msiof0_ss1_b), + SH_PFC_PIN_GROUP(msiof0_ss2_b), + SH_PFC_PIN_GROUP(msiof0_rx_b), + SH_PFC_PIN_GROUP(msiof0_tx_b), + SH_PFC_PIN_GROUP(msiof0_clk_c), + SH_PFC_PIN_GROUP(msiof0_sync_c), + SH_PFC_PIN_GROUP(msiof0_ss1_c), + SH_PFC_PIN_GROUP(msiof0_ss2_c), + SH_PFC_PIN_GROUP(msiof0_rx_c), + SH_PFC_PIN_GROUP(msiof0_tx_c), SH_PFC_PIN_GROUP(msiof1_clk), SH_PFC_PIN_GROUP(msiof1_sync), SH_PFC_PIN_GROUP(msiof1_ss1), SH_PFC_PIN_GROUP(msiof1_ss2), SH_PFC_PIN_GROUP(msiof1_rx), SH_PFC_PIN_GROUP(msiof1_tx), + SH_PFC_PIN_GROUP(msiof1_clk_b), + SH_PFC_PIN_GROUP(msiof1_sync_b), + SH_PFC_PIN_GROUP(msiof1_ss1_b), + SH_PFC_PIN_GROUP(msiof1_ss2_b), + SH_PFC_PIN_GROUP(msiof1_rx_b), + SH_PFC_PIN_GROUP(msiof1_tx_b), + SH_PFC_PIN_GROUP(msiof1_clk_c), + SH_PFC_PIN_GROUP(msiof1_sync_c), + SH_PFC_PIN_GROUP(msiof1_rx_c), + SH_PFC_PIN_GROUP(msiof1_tx_c), + SH_PFC_PIN_GROUP(msiof1_clk_d), + SH_PFC_PIN_GROUP(msiof1_sync_d), + SH_PFC_PIN_GROUP(msiof1_ss1_d), + SH_PFC_PIN_GROUP(msiof1_rx_d), + SH_PFC_PIN_GROUP(msiof1_tx_d), + SH_PFC_PIN_GROUP(msiof1_clk_e), + SH_PFC_PIN_GROUP(msiof1_sync_e), + SH_PFC_PIN_GROUP(msiof1_rx_e), + SH_PFC_PIN_GROUP(msiof1_tx_e), SH_PFC_PIN_GROUP(msiof2_clk), SH_PFC_PIN_GROUP(msiof2_sync), SH_PFC_PIN_GROUP(msiof2_ss1), SH_PFC_PIN_GROUP(msiof2_ss2), SH_PFC_PIN_GROUP(msiof2_rx), SH_PFC_PIN_GROUP(msiof2_tx), + SH_PFC_PIN_GROUP(msiof2_clk_b), + SH_PFC_PIN_GROUP(msiof2_sync_b), + SH_PFC_PIN_GROUP(msiof2_ss1_b), + SH_PFC_PIN_GROUP(msiof2_ss2_b), + SH_PFC_PIN_GROUP(msiof2_rx_b), + SH_PFC_PIN_GROUP(msiof2_tx_b), + SH_PFC_PIN_GROUP(msiof2_clk_c), + SH_PFC_PIN_GROUP(msiof2_sync_c), + SH_PFC_PIN_GROUP(msiof2_rx_c), + SH_PFC_PIN_GROUP(msiof2_tx_c), + SH_PFC_PIN_GROUP(msiof2_clk_d), + SH_PFC_PIN_GROUP(msiof2_sync_d), + SH_PFC_PIN_GROUP(msiof2_ss1_d), + SH_PFC_PIN_GROUP(msiof2_ss2_d), + SH_PFC_PIN_GROUP(msiof2_rx_d), + SH_PFC_PIN_GROUP(msiof2_tx_d), + SH_PFC_PIN_GROUP(msiof2_clk_e), + SH_PFC_PIN_GROUP(msiof2_sync_e), + SH_PFC_PIN_GROUP(msiof2_rx_e), + SH_PFC_PIN_GROUP(msiof2_tx_e), + SH_PFC_PIN_GROUP(qspi_ctrl), + SH_PFC_PIN_GROUP(qspi_data2), + SH_PFC_PIN_GROUP(qspi_data4), + SH_PFC_PIN_GROUP(qspi_ctrl_b), + SH_PFC_PIN_GROUP(qspi_data2_b), + SH_PFC_PIN_GROUP(qspi_data4_b), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_data_b), SH_PFC_PIN_GROUP(scif0_data_c), @@ -3337,6 +3858,18 @@ static const char * const i2c4_groups[] = { "i2c4_c", }; +static const char * const i2c7_groups[] = { + "i2c7", + "i2c7_b", + "i2c7_c", +}; + +static const char * const i2c8_groups[] = { + "i2c8", + "i2c8_b", + "i2c8_c", +}; + static const char * const intc_groups[] = { "intc_irq0", "intc_irq1", @@ -3358,6 +3891,18 @@ static const char * const msiof0_groups[] = { "msiof0_ss2", "msiof0_rx", "msiof0_tx", + "msiof0_clk_b", + "msiof0_sync_b", + "msiof0_ss1_b", + "msiof0_ss2_b", + "msiof0_rx_b", + "msiof0_tx_b", + "msiof0_clk_c", + "msiof0_sync_c", + "msiof0_ss1_c", + "msiof0_ss2_c", + "msiof0_rx_c", + "msiof0_tx_c", }; static const char * const msiof1_groups[] = { @@ -3367,6 +3912,25 @@ static const char * const msiof1_groups[] = { "msiof1_ss2", "msiof1_rx", "msiof1_tx", + "msiof1_clk_b", + "msiof1_sync_b", + "msiof1_ss1_b", + "msiof1_ss2_b", + "msiof1_rx_b", + "msiof1_tx_b", + "msiof1_clk_c", + "msiof1_sync_c", + "msiof1_rx_c", + "msiof1_tx_c", + "msiof1_clk_d", + "msiof1_sync_d", + "msiof1_ss1_d", + "msiof1_rx_d", + "msiof1_tx_d", + "msiof1_clk_e", + "msiof1_sync_e", + "msiof1_rx_e", + "msiof1_tx_e", }; static const char * const msiof2_groups[] = { @@ -3376,6 +3940,35 @@ static const char * const msiof2_groups[] = { "msiof2_ss2", "msiof2_rx", "msiof2_tx", + "msiof2_clk_b", + "msiof2_sync_b", + "msiof2_ss1_b", + "msiof2_ss2_b", + "msiof2_rx_b", + "msiof2_tx_b", + "msiof2_clk_c", + "msiof2_sync_c", + "msiof2_rx_c", + "msiof2_tx_c", + "msiof2_clk_d", + "msiof2_sync_d", + "msiof2_ss1_d", + "msiof2_ss2_d", + "msiof2_rx_d", + "msiof2_tx_d", + "msiof2_clk_e", + "msiof2_sync_e", + "msiof2_rx_e", + "msiof2_tx_e", +}; + +static const char * const qspi_groups[] = { + "qspi_ctrl", + "qspi_data2", + "qspi_data4", + "qspi_ctrl_b", + "qspi_data2_b", + "qspi_data4_b", }; static const char * const scif0_groups[] = { @@ -3568,11 +4161,14 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c4), + SH_PFC_FUNCTION(i2c7), + SH_PFC_FUNCTION(i2c8), SH_PFC_FUNCTION(intc), SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), |