diff options
author | Paul Mundt <lethal@linux-sh.org> | 2011-03-17 07:44:08 (GMT) |
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committer | Paul Mundt <lethal@linux-sh.org> | 2011-03-17 07:44:08 (GMT) |
commit | 1d2a1959fe534279cf37aba20b08c24c20840e52 (patch) | |
tree | 67c0b9aa7fe22a44bf0b4af88947799203eb8f67 /drivers/staging/ath6kl/include/target_reg_table.h | |
parent | 5a79ce76e9bb8f4b2cd8106ee36d15ee05013bcf (diff) | |
parent | 054cfaacf88865bff1dd58d305443d5d6c068a08 (diff) | |
download | linux-1d2a1959fe534279cf37aba20b08c24c20840e52.tar.xz |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 into sh-latest
Diffstat (limited to 'drivers/staging/ath6kl/include/target_reg_table.h')
-rw-r--r-- | drivers/staging/ath6kl/include/target_reg_table.h | 84 |
1 files changed, 42 insertions, 42 deletions
diff --git a/drivers/staging/ath6kl/include/target_reg_table.h b/drivers/staging/ath6kl/include/target_reg_table.h index 901f923..e2225d5 100644 --- a/drivers/staging/ath6kl/include/target_reg_table.h +++ b/drivers/staging/ath6kl/include/target_reg_table.h @@ -30,48 +30,48 @@ /*** WARNING : Add to the end of the TABLE! do not change the order ****/ typedef struct targetdef_s { - A_UINT32 d_RTC_BASE_ADDRESS; - A_UINT32 d_SYSTEM_SLEEP_OFFSET; - A_UINT32 d_SYSTEM_SLEEP_DISABLE_LSB; - A_UINT32 d_SYSTEM_SLEEP_DISABLE_MASK; - A_UINT32 d_CLOCK_CONTROL_OFFSET; - A_UINT32 d_CLOCK_CONTROL_SI0_CLK_MASK; - A_UINT32 d_RESET_CONTROL_OFFSET; - A_UINT32 d_RESET_CONTROL_SI0_RST_MASK; - A_UINT32 d_GPIO_BASE_ADDRESS; - A_UINT32 d_GPIO_PIN0_OFFSET; - A_UINT32 d_GPIO_PIN1_OFFSET; - A_UINT32 d_GPIO_PIN0_CONFIG_MASK; - A_UINT32 d_GPIO_PIN1_CONFIG_MASK; - A_UINT32 d_SI_CONFIG_BIDIR_OD_DATA_LSB; - A_UINT32 d_SI_CONFIG_BIDIR_OD_DATA_MASK; - A_UINT32 d_SI_CONFIG_I2C_LSB; - A_UINT32 d_SI_CONFIG_I2C_MASK; - A_UINT32 d_SI_CONFIG_POS_SAMPLE_LSB; - A_UINT32 d_SI_CONFIG_POS_SAMPLE_MASK; - A_UINT32 d_SI_CONFIG_INACTIVE_CLK_LSB; - A_UINT32 d_SI_CONFIG_INACTIVE_CLK_MASK; - A_UINT32 d_SI_CONFIG_INACTIVE_DATA_LSB; - A_UINT32 d_SI_CONFIG_INACTIVE_DATA_MASK; - A_UINT32 d_SI_CONFIG_DIVIDER_LSB; - A_UINT32 d_SI_CONFIG_DIVIDER_MASK; - A_UINT32 d_SI_BASE_ADDRESS; - A_UINT32 d_SI_CONFIG_OFFSET; - A_UINT32 d_SI_TX_DATA0_OFFSET; - A_UINT32 d_SI_TX_DATA1_OFFSET; - A_UINT32 d_SI_RX_DATA0_OFFSET; - A_UINT32 d_SI_RX_DATA1_OFFSET; - A_UINT32 d_SI_CS_OFFSET; - A_UINT32 d_SI_CS_DONE_ERR_MASK; - A_UINT32 d_SI_CS_DONE_INT_MASK; - A_UINT32 d_SI_CS_START_LSB; - A_UINT32 d_SI_CS_START_MASK; - A_UINT32 d_SI_CS_RX_CNT_LSB; - A_UINT32 d_SI_CS_RX_CNT_MASK; - A_UINT32 d_SI_CS_TX_CNT_LSB; - A_UINT32 d_SI_CS_TX_CNT_MASK; - A_UINT32 d_BOARD_DATA_SZ; - A_UINT32 d_BOARD_EXT_DATA_SZ; + u32 d_RTC_BASE_ADDRESS; + u32 d_SYSTEM_SLEEP_OFFSET; + u32 d_SYSTEM_SLEEP_DISABLE_LSB; + u32 d_SYSTEM_SLEEP_DISABLE_MASK; + u32 d_CLOCK_CONTROL_OFFSET; + u32 d_CLOCK_CONTROL_SI0_CLK_MASK; + u32 d_RESET_CONTROL_OFFSET; + u32 d_RESET_CONTROL_SI0_RST_MASK; + u32 d_GPIO_BASE_ADDRESS; + u32 d_GPIO_PIN0_OFFSET; + u32 d_GPIO_PIN1_OFFSET; + u32 d_GPIO_PIN0_CONFIG_MASK; + u32 d_GPIO_PIN1_CONFIG_MASK; + u32 d_SI_CONFIG_BIDIR_OD_DATA_LSB; + u32 d_SI_CONFIG_BIDIR_OD_DATA_MASK; + u32 d_SI_CONFIG_I2C_LSB; + u32 d_SI_CONFIG_I2C_MASK; + u32 d_SI_CONFIG_POS_SAMPLE_LSB; + u32 d_SI_CONFIG_POS_SAMPLE_MASK; + u32 d_SI_CONFIG_INACTIVE_CLK_LSB; + u32 d_SI_CONFIG_INACTIVE_CLK_MASK; + u32 d_SI_CONFIG_INACTIVE_DATA_LSB; + u32 d_SI_CONFIG_INACTIVE_DATA_MASK; + u32 d_SI_CONFIG_DIVIDER_LSB; + u32 d_SI_CONFIG_DIVIDER_MASK; + u32 d_SI_BASE_ADDRESS; + u32 d_SI_CONFIG_OFFSET; + u32 d_SI_TX_DATA0_OFFSET; + u32 d_SI_TX_DATA1_OFFSET; + u32 d_SI_RX_DATA0_OFFSET; + u32 d_SI_RX_DATA1_OFFSET; + u32 d_SI_CS_OFFSET; + u32 d_SI_CS_DONE_ERR_MASK; + u32 d_SI_CS_DONE_INT_MASK; + u32 d_SI_CS_START_LSB; + u32 d_SI_CS_START_MASK; + u32 d_SI_CS_RX_CNT_LSB; + u32 d_SI_CS_RX_CNT_MASK; + u32 d_SI_CS_TX_CNT_LSB; + u32 d_SI_CS_TX_CNT_MASK; + u32 d_BOARD_DATA_SZ; + u32 d_BOARD_EXT_DATA_SZ; } TARGET_REGISTER_TABLE; #define BOARD_DATA_SZ_MAX 2048 |