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author | Soren Brinkmann <soren.brinkmann@xilinx.com> | 2014-10-02 16:13:35 (GMT) |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2014-10-20 02:29:26 (GMT) |
commit | 812283cd54637633c1b5aa8d86667afe6c507f0e (patch) | |
tree | 6436908422b3ec1a3abccdb0d6024040c575f538 /drivers/staging/clocking-wizard/dt-binding.txt | |
parent | 6232876b723bb7954dd23405963155d8fb8dd654 (diff) | |
download | linux-812283cd54637633c1b5aa8d86667afe6c507f0e.tar.xz |
staging: Add Xilinx Clocking Wizard driver
Add a driver for the Xilinx Clocking Wizard soft IP. The clocking wizard
provides an AXI interface to dynamically reconfigure the clocking
resources of Xilinx FPGAs.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/clocking-wizard/dt-binding.txt')
-rw-r--r-- | drivers/staging/clocking-wizard/dt-binding.txt | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/staging/clocking-wizard/dt-binding.txt b/drivers/staging/clocking-wizard/dt-binding.txt new file mode 100644 index 0000000..723271e --- /dev/null +++ b/drivers/staging/clocking-wizard/dt-binding.txt @@ -0,0 +1,30 @@ +Binding for Xilinx Clocking Wizard IP Core + +This binding uses the common clock binding[1]. Details about the devices can be +found in the product guide[2]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Clocking Wizard Product Guide +http://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1/pg065-clk-wiz.pdf + +Required properties: + - compatible: Must be 'xlnx,clocking-wizard' + - reg: Base and size of the cores register space + - clocks: Handle to input clock + - clock-names: Tuple containing 'clk_in1' and 's_axi_aclk' + - clock-output-names: Names for the output clocks + +Optional properties: + - speed-grade: Speed grade of the device (valid values are 1..3) + +Example: + clock-generator@40040000 { + reg = <0x40040000 0x1000>; + compatible = "xlnx,clocking-wizard"; + speed-grade = <1>; + clock-names = "clk_in1", "s_axi_aclk"; + clocks = <&clkc 15>, <&clkc 15>; + clock-output-names = "clk_out0", "clk_out1", "clk_out2", + "clk_out3", "clk_out4", "clk_out5", + "clk_out6", "clk_out7"; + }; |