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authorToshiaki Yamane <yamanetoshi@gmail.com>2012-09-07 04:27:38 (GMT)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2012-09-10 22:36:04 (GMT)
commitf6c608910ebfa53c98aee34eeb5a00829c970025 (patch)
tree63f4925bc443be083faf6a90ac35827cf6b883c1 /drivers/staging/rts_pstor
parentff514c1c53fb2a839b4a419df8e265ebb3facc95 (diff)
downloadlinux-f6c608910ebfa53c98aee34eeb5a00829c970025.tar.xz
staging/rts_pstor: remove braces {} in sd.c (sd_change_phase)
fixed below checkpatch warnings. -WARNING: braces {} are not necessary for any arm of this statement -WARNING: braces {} are not necessary for single statement blocks Signed-off-by: Toshiaki Yamane <yamanetoshi@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/rts_pstor')
-rw-r--r--drivers/staging/rts_pstor/sd.c20
1 files changed, 9 insertions, 11 deletions
diff --git a/drivers/staging/rts_pstor/sd.c b/drivers/staging/rts_pstor/sd.c
index 6badbc4..67420f4 100644
--- a/drivers/staging/rts_pstor/sd.c
+++ b/drivers/staging/rts_pstor/sd.c
@@ -866,9 +866,8 @@ static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir)
if (tune_dir == TUNE_RX) {
SD_VP_CTL = SD_VPRX_CTL;
SD_DCMPS_CTL = SD_DCMPS_RX_CTL;
- if (CHK_SD_DDR50(sd_card)) {
+ if (CHK_SD_DDR50(sd_card))
ddr_rx = 1;
- }
} else {
SD_VP_CTL = SD_VPTX_CTL;
SD_DCMPS_CTL = SD_DCMPS_TX_CTL;
@@ -905,23 +904,22 @@ static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir)
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE, DCMPS_CHANGE);
rtsx_add_cmd(chip, CHECK_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE_DONE, DCMPS_CHANGE_DONE);
retval = rtsx_send_cmd(chip, SD_CARD, 100);
- if (retval != STATUS_SUCCESS) {
+ if (retval != STATUS_SUCCESS)
TRACE_GOTO(chip, Fail);
- }
val = *rtsx_get_cmd_data(chip);
- if (val & DCMPS_ERROR) {
+ if (val & DCMPS_ERROR)
TRACE_GOTO(chip, Fail);
- }
- if ((val & DCMPS_CURRENT_PHASE) != sample_point) {
+
+ if ((val & DCMPS_CURRENT_PHASE) != sample_point)
TRACE_GOTO(chip, Fail);
- }
+
RTSX_WRITE_REG(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
- if (ddr_rx) {
+ if (ddr_rx)
RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, 0);
- } else {
+ else
RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0);
- }
+
udelay(50);
}