serial: 8250: Tolerate clock variance for max baud rate

When the UART clock is set slightly under 1.8432MHz, the 8250 driver
core doesn't permit the 115200 baud rate since it calculates the maximum
frequency to pass to uart_get_baud_rate by simply dividing the uart
clock by 16 which yields a value slightly under 115200, even though the
frequency is close enough for the UART to operate reliably.

Therefore add some tolerance in the calculation of the maximum baud
rate. 1% tolerance allows for marginally slower uart clk than nominal
without introducing transmission errors.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
[pjh: Forward-port & refactor original patch; change tolerance to 1%]
Signed-off-by: Peter Hurley <peter@hurleysoftware.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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