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authorJames Morris <jmorris@namei.org>2008-12-04 06:16:36 (GMT)
committerJames Morris <jmorris@namei.org>2008-12-04 06:16:36 (GMT)
commitec98ce480ada787f2cfbd696980ff3564415505b (patch)
tree1a4d644b38f9f1e4b4e086fde0b195df4a92cf84 /drivers/video/aty/radeon_accel.c
parent3496f92beb9aa99ef21fccc154a36c7698e9c538 (diff)
parentfeaf3848a813a106f163013af6fcf6c4bfec92d9 (diff)
downloadlinux-ec98ce480ada787f2cfbd696980ff3564415505b.tar.xz
Merge branch 'master' into next
Conflicts: fs/nfsd/nfs4recover.c Manually fixed above to use new creds API functions, e.g. nfs4_save_creds(). Signed-off-by: James Morris <jmorris@namei.org>
Diffstat (limited to 'drivers/video/aty/radeon_accel.c')
-rw-r--r--drivers/video/aty/radeon_accel.c21
1 files changed, 12 insertions, 9 deletions
diff --git a/drivers/video/aty/radeon_accel.c b/drivers/video/aty/radeon_accel.c
index 8718f73..a547e5d 100644
--- a/drivers/video/aty/radeon_accel.c
+++ b/drivers/video/aty/radeon_accel.c
@@ -174,12 +174,12 @@ static void radeonfb_prim_imageblit(struct radeonfb_info *rinfo,
const struct fb_image *image,
u32 fg, u32 bg)
{
- unsigned int src_bytes, dwords;
+ unsigned int dwords;
u32 *bits;
radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache,
rinfo->dp_gui_mc_base |
- GMC_BRUSH_NONE |
+ GMC_BRUSH_NONE | GMC_DST_CLIP_LEAVE |
GMC_SRC_DATATYPE_MONO_FG_BG |
ROP3_S |
GMC_BYTE_ORDER_MSB_TO_LSB |
@@ -189,9 +189,6 @@ static void radeonfb_prim_imageblit(struct radeonfb_info *rinfo,
radeonfb_set_creg(rinfo, DP_SRC_FRGD_CLR, &rinfo->dp_src_fg_cache, fg);
radeonfb_set_creg(rinfo, DP_SRC_BKGD_CLR, &rinfo->dp_src_bg_cache, bg);
- radeon_fifo_wait(rinfo, 1);
- OUTREG(DST_Y_X, (image->dy << 16) | image->dx);
-
/* Ensure the dst cache is flushed and the engine idle before
* issuing the operation.
*
@@ -205,13 +202,19 @@ static void radeonfb_prim_imageblit(struct radeonfb_info *rinfo,
/* X here pads width to a multiple of 32 and uses the clipper to
* adjust the result. Is that really necessary ? Things seem to
- * work ok for me without that and the doco doesn't seem to imply
+ * work ok for me without that and the doco doesn't seem to imply]
* there is such a restriction.
*/
- OUTREG(DST_WIDTH_HEIGHT, (image->width << 16) | image->height);
+ radeon_fifo_wait(rinfo, 4);
+ OUTREG(SC_TOP_LEFT, (image->dy << 16) | image->dx);
+ OUTREG(SC_BOTTOM_RIGHT, ((image->dy + image->height) << 16) |
+ (image->dx + image->width));
+ OUTREG(DST_Y_X, (image->dy << 16) | image->dx);
+
+ OUTREG(DST_HEIGHT_WIDTH, (image->height << 16) | ((image->width + 31) & ~31));
- src_bytes = (((image->width * image->depth) + 7) / 8) * image->height;
- dwords = (src_bytes + 3) / 4;
+ dwords = (image->width + 31) >> 5;
+ dwords *= image->height;
bits = (u32*)(image->data);
while(dwords >= 8) {