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authorShaik Ameer Basha <shaik.ameer@samsung.com>2014-05-08 11:28:01 (GMT)
committerTomasz Figa <t.figa@samsung.com>2014-05-14 17:40:22 (GMT)
commit58ff8d038338bc0371da704f76faaa5769db68c3 (patch)
treea3365d2e0121c4336051384e2f516e484aece558 /drivers
parent1d87db4d4e05f6f0c5343cfcafc4234fe59e3cd1 (diff)
downloadlinux-58ff8d038338bc0371da704f76faaa5769db68c3.tar.xz
clk: samsung: exynos5420: fix register offset for sclk_bpll
This patch fixes the wrong register offset for sclk_bpll clock. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index e48f6f8..2171366 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -111,7 +111,6 @@
#define TOP_SPARE2 0x10b08
#define BPLL_LOCK 0x20010
#define BPLL_CON0 0x20110
-#define SRC_CDREX 0x20200
#define KPLL_LOCK 0x28000
#define KPLL_CON0 0x28100
#define SRC_KFC 0x28200
@@ -204,7 +203,6 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
GATE_TOP_SCLK_FSYS,
GATE_TOP_SCLK_PERIC,
TOP_SPARE2,
- SRC_CDREX,
SRC_KFC,
DIV_KFC0,
};
@@ -380,7 +378,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
- MUX(0, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
+ MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
MUX_A(0, "mout_aclk400_mscl", mout_group1_p,