clk: qoriq: add more divider clocks support

More divider clocks are needed for IP use. So enlarge the PLL divider
array to accommodate more divider clocks.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>

1 files changed, 8 insertions, 1 deletions

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 0e7de00..d62ccb2 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -41,7 +41,7 @@ struct clockgen_pll_div {
 };
 
 struct clockgen_pll {
-	struct clockgen_pll_div div[4];
+	struct clockgen_pll_div div[8];
 };
 
 #define CLKSEL_VALID	1
@@ -1127,6 +1127,13 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
 		struct clk *clk;
 		int ret;
 
+		/*
+		 * For platform PLL, there are 8 divider clocks.
+		 * For core PLL, there are 4 divider clocks at most.
+		 */
+		if (idx != 0 && i >= 4)
+			break;
+
 		snprintf(pll->div[i].name, sizeof(pll->div[i].name),
 			 "cg-pll%d-div%d", idx, i + 1);