diff options
| author | Leilk Liu <leilk.liu@mediatek.com> | 2015-08-24 03:45:18 (GMT) |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2015-08-25 17:48:23 (GMT) |
| commit | 2ce0acf5673e7ee82506e69109876e037e4a64be (patch) | |
| tree | 4ae5e6d1c9405c326b3921c01806103be0513c9c /drivers | |
| parent | 13da5a0b72ea66c74483966ff91718ae0a9c0703 (diff) | |
| download | linux-2ce0acf5673e7ee82506e69109876e037e4a64be.tar.xz | |
spi: mediatek: replace *_time name
This patch replaces *_time name in mtk_spi_prepare_transfer().
Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/spi/spi-mt65xx.c | 20 |
1 files changed, 8 insertions, 12 deletions
diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c index 14112a5..c1e96d3 100644 --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c @@ -238,8 +238,7 @@ static void mtk_spi_set_cs(struct spi_device *spi, bool enable) static void mtk_spi_prepare_transfer(struct spi_master *master, struct spi_transfer *xfer) { - u32 spi_clk_hz, div, high_time, low_time, holdtime, - setuptime, cs_idletime, reg_val = 0; + u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0; struct mtk_spi *mdata = spi_master_get_devdata(master); spi_clk_hz = clk_get_rate(mdata->spi_clk); @@ -248,21 +247,18 @@ static void mtk_spi_prepare_transfer(struct spi_master *master, else div = 1; - high_time = (div + 1) / 2; - low_time = (div + 1) / 2; - holdtime = (div + 1) / 2 * 2; - setuptime = (div + 1) / 2 * 2; - cs_idletime = (div + 1) / 2 * 2; + sck_time = (div + 1) / 2; + cs_time = sck_time * 2; - reg_val |= (((high_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET); - reg_val |= (((low_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); - reg_val |= (((holdtime - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); - reg_val |= (((setuptime - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET); + reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET); + reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); + reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); + reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET); writel(reg_val, mdata->base + SPI_CFG0_REG); reg_val = readl(mdata->base + SPI_CFG1_REG); reg_val &= ~SPI_CFG1_CS_IDLE_MASK; - reg_val |= (((cs_idletime - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); + reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); writel(reg_val, mdata->base + SPI_CFG1_REG); } |